參數(shù)資料
型號(hào)： 22363A
英文描述： Simple System Interface for UltraNAND Flash
中文描述： 簡(jiǎn)單的系統(tǒng)接口UltraNAND閃光
文件頁(yè)數(shù)： 4/21頁(yè)
文件大?。?/td> 725K
代理商： 22363A
Simple System Interface for UltraNAND Flash
3
System Interface Signal Description
The UltraNAND Interface PLD is responsible for gener-
ating the signals required by the UltraNAND device,
which are not found in typical systems. These are CLE,
ALE, WE#, RE#, SE#, and WP#. In order to control the
Interface PLD, the system is responsible for providing
some of the more typical address and control signals.
The definition of all pertinent signals, and the source
required to generate the signals, are included in Table
1. A timing diagram of a Read First Half Page opera-
tion is shown in Figure 2, and includes all of the signals
required by UltraNAND.
Table 1.
UltraNAND System Interface Signal Description
Figure 2.
UltraNAND Read First Half Page Timing Diagram
Signal
Source
Definition
INIT
Optional Boot Loader
PLD
From optional “Boot Loader for Simple System Interface” PLD to indicate that
the Boot Loader PLD is initializing UltraNAND
ALE
Interface PLD
Address Latch Enable required for address latch cycles
CLE
Interface PLD
Command Latch Enable required to latch the command
OUTCE[0..2]#
Interface PLD
The Chip Enables used to select the UltraNAND bank(s)
RE#
Interface PLD
Read signal used by UltraNAND for all read cycles
READY
Interface PLD
Tri-state output to allow the system to read the state of the RY/BY# pin(s)
SE#
Interface PLD
Spare Area Enable to control access to the UltraNAND spare area
WE#
Interface PLD
Write signal used by UltraNAND for all write cycles
WP#
Interface PLD
Write Protect to prevent program/erase operations in UltraNAND
A[0..3]
System
Address bus used to select one of sixteen Interface PLD control ports
CE#
System
The Chip Enable used to select the UltraNAND and Interface PLD
I/O[0..7]
System/UltraNAND
The eight I/O lines used to transfer commands, addresses, and data
RESET
System
A system reset signal which remains high until V
CC
is valid
READ#
System
Read signal used by the system for all read cycles
WRITE#
System
Write signal used by the system for all write cycles
RY/BY#
UltraNAND
Ready/Busy signal to indicate the current state of UltraNAND
OUTCE#
RY/BY#
WP#
SE#
I/O[0..7]
RE#
WE#
ALE
CLE
00h
A0-A7
A9-A16
A17-A24
Dout N
Dout 527
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