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參數(shù)資料
| 型號： | 22363A |
| 英文描述： | Simple System Interface for UltraNAND Flash |
| 中文描述： | 簡單的系統(tǒng)接口UltraNAND閃光 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 725K |
| 代理商： | 22363A |
4
Simple System Interface for UltraNAND Flash
Interface PLD Port Addresses
The UltraNAND Interface PLD occupies sixteen port
addresses. The port address locations are determined
by the CE# (Chip Enable) signal generated by the sys-
tem. This allows the UltraNAND device, or devices, to
be set up as either a memory mapped or I/O mapped
system resource. The system sets the base address of
the device through the chip enable address decode
and the UltraNAND interface will then be accessible at
that address, and through the next fifteen sequential
addresses. As an example, if the chip enable decode
is set for I/O location 200h, the Interface PLD would re-
side at I/O locations 200h through 20Fh. A description
of each interface address and the operation performed
is included in Table 2.
Table 2.
UltraNAND System Interface Control Port Definition
Legend:
X = Don’t Care
Interface PLD Theory of Operation
This section describes the functional blocks of the In-
terface PLD. The example AmPALLV16V8 and
AmPALLV22V10 PLDs generated are shown in Figure
4 and Figure 5 respectively. An application schematic
for three UltraNAND devices, supported by a single
AmPALLV22V10 PLD, is shown in Figure 6.
Port Decode
In the simple system interface design PLD examples,
combinatorial logic is used to perform the basic port ad-
dress decode function. This allows the Interface PLD
to respond to address decodes 00h through 0Fh as an
offset from the base address determined by the CE# in-
put. The decoder logic outputs are used to determine
when to drive the CLE, RE#, and WE# signals to Ul-
traNAND directly, to set and clear transparent latches
for ALE, OUTCE[0..2]#, SE#, and WP#, or to allow the
system to read the state of the RY/BY# pin through the
Interface PLD READY output.
Port
Read
Write
Operation Performed
0
Data, ID, or Status
Address or Data
Read information depends on previous command loaded
Write addresses (ALE = high) or data (ALE = low)
1
N/A
Command
All commands are written through this port with ALE cleared (low)
2
N/A
Set ALE
Set ALE (high) to allow addresses to be written
3
N/A
Clear ALE
Clear ALE (low) to allow commands, or data, to be written
4
N/A
Set SE#
Set SE# (low) to allow access to the spare area of each page
5
N/A
Clear SE#
Clear SE# (high) to prevent access to the spare area of each page
6
N/A
Set WP#
Set WP# (low) to prevent program/erase cycles
7
N/A
Clear WP#
Clear WP# (high) to allow program/erase cycles
8
N/A
Set CE0#
Set CE0# (low) to enable the first UltraNAND bank
9
N/A
Clear CE0#
Clear CE0# (high) to disable the first UltraNAND bank
A
N/A
Set CE1#
Set CE1# (low) to enable the second UltraNAND bank
B
N/A
Clear CE1#
Clear CE1# (high) to disable the second UltraNAND bank
C
N/A
Set CE2#
Set CE2# (low) to enable the third UltraNAND bank
D
N/A
Clear CE2#
Clear CE2# (high) to disable the third UltraNAND bank
E
N/A
N/A
No Function
F
RY/BY# Status
N/A
Read the state of all RY/BY# pins through this port
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