Simple System Interface for UltraNAND Flash
17
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
V0015 */ 0 1 1 0 0 0 1 0 0 1
V0016 */ 0 0 1 0 0 0 0 0 0 1
V0017 */ 0 1 1 0 0 0 0 0 0 1
V0018 */ 0 0 1 0 0 0 0 0 0 1
V0019 */ 0 1 1 0 0 0 0 0 0 1
V0020 */ 0 0 1 0 0 0 0 0 0 1
V0021 */ 0 1 1 0 0 0 0 0 0 1
V0022 */ 0 0 1 0 0 0 0 0 0 1
V0023 */ 0 1 1 0 0 0 0 0 0 1
V0024 */ 0 0 1 0 0 0 1 1 0 1
V0025 */ 0 1 1 0 0 0 1 1 0 1
V0026 */ 0 0 1 0 0 1 0 1 0 1
V0027 */ 0 1 1 0 0 1 0 1 0 1
V0028 */ 0 0 1 0 0 1 1 1 0 1
V0029 */ 0 1 1 0 0 1 1 1 0 1
V0030 */ 0 0 1 0 0 0 0 0 0 1
V0031 */ 0 1 1 0 0 0 0 0 0 1
V0032 */ 0 0 1 0 0 0 0 0 0 1
V0033 */ 0 1 1 0 0 0 0 0 0 1
V0034 */ 0 0 1 0 0 1 1 0 0 1
V0035 */ 0 1 1 0 0 1 1 0 0 1
V0036 */ 0 0 1 0 0 0 0 1 0 1
V0037 */ 0 1 1 0 0 0 0 1 0 1
V0038 */ 0 0 1 0 0 0 1 0 0 1
V0039 */ 0 1 1 0 0 0 1 0 0 1
V0040 */ 0 0 1 0 0 0 0 0 0 1
V0041 */ 0 1 1 0 0 0 0 0 0 1
V0042 */ 0 0 1 0 0 0 0 0 0 1
V0043 */ 0 1 1 0 0 0 0 0 0 1
V0044 */ 0 0 1 0 0 0 0 0 0 1
V0045 */ 0 1 1 0 0 0 0 0 0 0
V0046 */ 0 0 1 0 0 0 1 1 0 0
V0047 */ 0 1 1 0 0 0 1 1 0 0
V0048 */ 0 0 1 0 0 1 0 0 0 0
V0049 */ 0 1 1 0 0 1 0 0 0 0
V0050 */ 0 1 0 0 1 1 1 1 0 0
V0051 */ 0 1 1 0 1 1 1 1 0 0
V0052 */ 0 1 0 0 1 1 1 1 0 0
V0053 */ 0 1 1 0 1 1 1 1 0 0
V0054 */ 0 1 0 0 1 1 1 1 0 0
V0055 */ 0 1 1 0 1 1 1 1 0 1
V0056 */ 0 1 0 0 1 1 1 1 0 1
V0057 */ 0 1 1 0 1 1 1 1 0 1
V0058 */ 0 1 0 0 0 0 0 0 0 1
V0059 */ 0 1 1 0 0 0 0 0 0 1
V0060 */ 0 1 0 0 0 0 0 0 0 1
V0061 */ 0 1 1 0 0 0 0 0 0 1
V0062 */ 0 0 1 0 0 1 0 1 0 1
V0063 */ 0 1 1 0 0 1 0 1 0 1
L H L L L L L H H Z /* idle
L H L L L L L L H Z /* Write address
L H L L L L L H H Z /* idle
L H L L L L L L H Z /* Write address
L H L L L L L H H Z /* idle
L H L L L L L L H Z /* Write address
L H L L L L L H H Z /* idle
L H L L L L L L H Z /* Write address
L H L L L L L H H Z /* idle
L L L L L L L H H Z /* Clear ALE
L L L L L L L H H Z /* idle
L L H L L L L H H Z /* Clear SE#
L L H L L L L H H Z /* idle
L L H H L L L H H Z /* Clear WP#
L L H H L L L H H Z /* idle
L L H H L L L L H Z /* Write data
L L H H L L L H H Z /* idle
L L H H L L L L H Z /* Write data
L L H H L L L H H Z /* idle
L L H L L L L H H Z /* Set WP#
L L H L L L L H H Z /* idle
H L H L L L L L H Z /* Write command-CLE */
H L H L L L L H H Z /* idle
L H H L L L L H H Z /* Set ALE
L H H L L L L H H Z /* idle
L H H L L L L L H Z /* Write address
L H H L L L L H H Z /* idle
L H H L L L L L H Z /* Write address
L H H L L L L H H Z /* idle
L H H L L L L L H Z /* Write address
L H H L L L L H H Z /* idle
L L H L L L L H H Z /* Clear ALE
L L H L L L L H H Z /* idle
L L L L L L L H H Z /* Set SE#
L L L L L L L H H Z /* idle
L L L L L L L H H L /* Read RY/BY# status */
L L L L L L L H H Z /* idle
L L L L L L L H H L /* Read RY/BY# status */
L L L L L L L H H Z /* idle
L L L L L L L H H L /* Read RY/BY# status */
L L L L L L L H H Z /* idle
L L L L L L L H H H /* Read RY/BY# status */
L L L L L L L H H Z /* idle
L L L L L L L H L Z /* Read data
L L L L L L L H H Z /* idle
L L L L L L L H L Z /* Read data
L L L L L L L H H Z /* idle
L L H L L L L H H Z /* Clear SE#
L L H L L L L H H Z /* idle
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/