Simple System Interface for UltraNAND Flash
11
PLD Simulation File for UNISA16
The simulation file included here is used to verify the design of the PLD supporting one UltraNAND bank.
Name UNISA16;
Partno PLD001;
Date 03/23/99;
Revision 0;
Designer Ralph Gibson;
Company Advanced Micro Devices;
Assembly UltraNAND(TM) ISA Development Board Interface Solution;
Location U1;
/************************************************************************\
** This is a simple interface for UltraNAND allowing one UltraNAND to **
** be supported on a PC ISA bus. This device includes a RESET input to **
** force WP# asserted on power transitions. RESET is high until Vcc **
** is valid and goes high when supply power ramps down. **
**************************************************************************
** Allowable Target Device Types: AmPALCE16V8-10 **
\************************************************************************/
ORDER: RESET, %1, !WRITE, %1, !READ, %1, !CE, %1,
A3, %1, A2, %1, A1, %1, A0, %1, INIT, %1, RY_BY, %2,
CLE, %1, ALE, %1, !SE, %1, !WP, %1, !OUTCE, %1,
!WE, %1, !RE, %1, READY;
VECTORS:
$msg
$msg
$msg
$msg
$msg
$msg
$msg
$msg
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
"
"
"
"
"
"
"
"
";
";
!
W !
R R
I E !
T A C A A A A I B
E D E 3 2 1 0 T Y
- - - - - - - - -
1 1 1 0 0 0 0 0 1
1 1 1 0 0 0 0 0 1
1 1 0 0 0 0 0 0 1
1 1 0 0 0 0 1 0 1
1 1 0 1 0 0 0 0 1
0 1 0 1 0 0 0 0 1
1 1 0 1 0 0 0 0 1
0 1 0 0 0 0 1 0 1
1 1 0 0 0 0 1 0 1
0 1 0 0 0 1 0 0 1
1 1 0 0 0 1 0 0 1
0 1 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 1
!
O
U
R
E
S
E
T
-
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R ";
E ";
I Y
N -
C A ! ! T ! ! A ";
L L S W C W R D ";
E E E P E E E Y ";
- - - - - - - -
L L L L H H H Z /* Reset the device
L L L L H H H Z /* Reset the device
L L L L H H H Z /* no function
H L L L H H H Z /* no function
L L L L H H H Z /* no function
L L L L L H H Z /* Set OUTCE#
L L L L L H H Z /* idle
H L L L L L H Z /* Write command - CLE
*/
H L L L L H H Z /* idle
L H L L L H H Z /* Set ALE
L H L L L H H Z /* idle
L H L L L L H Z /* Write address
L H L L L H H Z /* idle
L H L L L L H Z /* Write address
L H L L L H H Z /* idle
V0001 */
V0002 */
V0003 */
V0004 */
V0005 */
V0006 */
V0007 */
V0008 */
V0009 */
V0010 */
V0011 */
V0012 */
V0013 */
V0014 */
V0015 */
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/