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參數(shù)資料
| 型號： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow??？技術(shù)平臺設(shè)計指南應(yīng)用指南“ |
| 文件頁數(shù)： | 10/50頁 |
| 文件大?。?/td> | 957K |
| 代理商： | 24267A |
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4
Enhanced Power Management Features
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
Figure 1. Enhanced Power Management Register (EPMR)
Table 2.
Enhanced Power Management Register (EPMR) Definition
Bit
Description
R/W
Function
1
All reserved bits are always read as 0.
IOBASE defines a base address for a 16-byte block of I/O address
space accessible for enabling, controlling, and monitoring the EPM
features.
All reserved bits are always read as 0.
This bit controls whether a special bus cycle is generated upon
dword accesses within the EPM 16-byte I/O block. If set to 1, an
EPM special bus cycle is generated, where BE[7:0]# = BFh and
A[4:3] = 00b.
This bit controls access to the I/O-mapped address space for the
AMD PowerNow! technology EPM features. Clearing this bit to
zero does not affect the state of bits defined in the EPM 16-byte I/O
block.
Notes:
1.
All bits default to 0 when RESET is asserted.
63–16
Reserved
R
15-4
I/O BASE Address (IOBASE)
R/W
3-2
Reserved
R
1
Generate Special Bus Cycle (GSBC)
R/W
0
Enable
AMD PowerNow! Technology
Management
(EN)
R/W
Reserved
0
16
63
15
4
3
1
2
E
N
G
S
B
C
IOBASE
Symbol Description
IOBASE I/O Base Address
GSBC
Generate Special Bus Cycle
EN
Enable AMD PowerNow! Technology
Management
Bit
5-4
1
0
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