
Enhanced Power Management Features
3
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
Enhanced Power Management Features
AMD-K6-2E+ and AMD-K6-IIIE+ low-power processors enabled
with AMD PowerNow! technology include two new features
specifically designed to enhance power management
functionality:
I
Dynamic core frequency control
Core voltage control
I
These enhanced power management (EPM) features are
accessed and controlled through an aligned 16-byte block of I/O
address space that is defined by a model-specific register
(MSR) called the Enhanced Power Management Register
(EPMR).
Enhanced Power Management Register (EPMR)
The EPMR register allows software to access the aligned EPM
16-byte block of I/O address space, which contains bits for
enabling, controlling, and monitoring the EPM features. All
accesses to the EPM 16-byte I/O block must be aligned dword
accesses. Valid accesses to the EPM 16-byte block do not
generate I/O cycles on the host bus, keeping EPMR accesses
local to the CPU, while non-aligned and non-dword accesses are
passed to the host bus.
Figure 1 on page 4 and Table 2 define the EPMR register. The
EPMR can be addressed at MSR location C000_0086h.
An assertion of RESET clears all of the bits of the 16-byte I/O
block to 0 (excluding the Voltage ID Output bits which default
to 01010b). BIOS or the real-time operating system (RTOS)
must always initialize the EPMR register and EPM features
after the processor comes out of RESET.