參數(shù)資料
型號(hào)： 24267A
英文描述： Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
中文描述： “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow??？技術(shù)平臺(tái)設(shè)計(jì)指南應(yīng)用指南“
文件頁數(shù)： 14/50頁
文件大小： 957K
代理商： 24267A
8
Dynamic Core Frequency and Core Voltage Control
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
Effective Bus Divisors EBF[2:0]
The processor core frequency is controlled by the Effective Bus
Frequency Divisor—EBF[2:0]—which dictates the processor-to-
bus clock ratio supplied to the processor’s internal PLL. This
processor-to-bus clock ratio is multiplied by the external bus
frequency to set the frequency of operation for the processor
core.
I
At the fall of RESET, the EBF[2:0] value is determined by
the state of the processor BF[2:0] input pins.
Afterwards, the EBF[2:0] value can be dynamically
controlled through AMD PowerNow! technology state
transitions.
I
Table 4 lists valid EBF[2:0] states and equivalent processor- to-
bus clock ratios.
Table 4.
Processor-to-Bus Clock Ratios
State of EBF[2:0]
100b
101b
110b
111b
000b
001b
010b
011b
Processor-to-Bus Clock Ratio
2.0x
1
3.0x
6.0x
3.5x
4.5x
5.0x
4.0x
5.5x
Notes:
1.
The 0.18-micron processors do not support the 2.5x ratio supported by earlier processors.
Instead, a ratio of 2.0x is selected when EBF[2:0] equals 100b
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