Software Implementation
31
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
Table 11.
AMD PowerNow! Technology Descriptor Table
Offset
0
Length
4
Description
Signature: “GBDT”
Length, in bytes, of the entire AMD PowerNow! technology BIOS descriptor table
(no larger than 256 bytes.)
AMD PowerNow! technology BIOS API revision in BCD. Tens = major, Ones = minor
Checksum; entire table must sum to zero
Reserved
Bus speed in binary MHz (66, 75, 83, 92, 100, 112, 133, 150, 200, etc.)
Maximum CPU frequency for current processor in binary MHz
Maximum AMD PowerNow! technology state support by system (“N”). There are N+1
possible states and N<16. The minimum state is always zero.
4
1
5
6
7
8
10
1
1
1
2
2
12
1
AMD PowerNow! Technology SMI Command Port Information
SMI Command Port Type/Size:
Bit 0: Address Space, where 0 = x86 I/O address, and 1 = memory-mapped address.
Bits 6–4: Data Size, where 001 = 8 bits (byte access), 010 = 16 bits, 100 = 32 bits.
Bits 3–1, 7, and 8 are reserved and must be 0.
Address of SMI command port
AMD PowerNow! Technology_Code (Load ESI register with this number before making SMI call.
Currently the code is defined as 9800_0089h.)
13
1
14
4
18
4
Voltage/Frequency to State Map for Current System
State 0 CPU Voltage (A.BCD format)
State 0 CPU Frequency (in binary MHz)
State 0 VID[4:0]
State 0 BF[2:0]
State 1 CPU Voltage
State 1 CPU Frequency
State 1 VID[4:0]
State 1 BF[2:0]
State 2 CPU Voltage
State 2 CPU Frequency
State 2 VID[4:0]
State 2 BF[2:0]
State N CPU Voltage
State N CPU Frequency
State N VID[4:0]
State N BF[2:0]
22
24
26
27
28
30
32
33
34
36
38
39
xx
xx
xx
xx
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1