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| 型號(hào)： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow！？技術(shù)平臺(tái)設(shè)計(jì)指南應(yīng)用指南“ |
| 文件頁數(shù)： | 12/50頁 |
| 文件大小： | 957K |
| 代理商： | 24267A |
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6
Enhanced Power Management Features
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
EPM 16-Byte I/O Block
The EPM 16-byte I/O block contains a single 4-byte field for
enabling, controlling, and monitoring the EPM features. This
Bus Divisor and Voltage ID Control (BVC) field (see Figure 2,
“Dynamic Core Frequency Control” on page 10, and Figure 3 on
page 11) is the control center for supported state transitions.
Table 3 defines the functions supported by each of the byte-
fields within the EPM 16-byte I/O block.
Figure 2. EPM 16-Byte I/O Block
Table 3.
EPM 16-Byte I/O Block Definition
Byte
Description
R/W
Function
1
All reserved bits are always read as 0.
The bit fields within the BVC bytes allow software to change the
processor bus divisor and core voltage. See “Dynamic Core Fre-
quency Control” on page 10 and Figure 3 on page 11 for detailed
information about this field.
All reserved bits are always read as 0.
Notes:
1.
All bits default to 0 when RESET is asserted
15-12
Reserved
R
11-8
Bus Divisor and Voltage ID Control (BVC)
R/W
7-0
Reserved
R
Reserved
0
12
15
11
8
7
BVC
Symbol Description
BVC
Bus Divisor and Voltage ID Control
Bytes
11-8
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