參數(shù)資料
型號： 24267A
英文描述： Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
中文描述： “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow??？技術(shù)平臺設(shè)計指南應(yīng)用指南“
文件頁數(shù)： 27/50頁
文件大小： 957K
代理商： 24267A
Hardware Implementation
21
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
Maximum Frequency
Initialization
(Recommended)
Systems that strap the processor BF[2:0] inputs so that the
processor runs at the highest supported frequency are set for
maximum
frequency.
I
The advantage of this implementation is that it does allow
the BIOS to directly determine the CPU’s maximum
frequency by the state of the BF[2:0] pins.
The disadvantage of this method is that it limits the number
of regulator VID[4:0] input combinations and the output
core voltage range available. It is also important to note that
the V
CC2
voltage will be initialized to 2.0 V.
I
If it is desired to have the processor run at its maximum
frequency whenever RESET is asserted, all of the processor’s
VID[4:0] outputs cannot be tied directly to the regulator’s
D[4:0] inputs using this method. A total one-to-one VID[4:0]
correspondence results in a core voltage supply of 1.5 V, which
does not guarantee functional operation conditions at the
processor’s maximum frequency.
In the case that the BF[2:0] inputs to the processor are strapped
to select the maximum CPU core frequency, additional logic is
required to translate the CPU’s default VID[4:0] output into a
regulator input that is interpreted as a voltage that provides
functional operation conditions at the processor’s maximum
frequency. The recommended solution is shown in Figure 4 on
page 19.
For a step-by-step example of how to modify an existing design
for this recommended implementation, see “VID[4:0]
Modification for Maximum BF[2:0] Boot Option” on page 24.
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