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參數(shù)資料
| 型號： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow??？技術(shù)平臺設(shè)計指南應(yīng)用指南“ |
| 文件頁數(shù)： | 20/50頁 |
| 文件大小： | 957K |
| 代理商： | 24267A |
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14
Dynamic Core Frequency and Core Voltage Control
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
Guaranteed CPU Core Voltage at Power On
The processor VID[4:0] outputs are initialized to a default state
of 01010b, but they are only initialized after RESET is asserted,
the CPU input clock is running, and an I/O voltage is applied.
As a result, it is necessary to drive the input select pins of the
DC/DC regulator from a source other than the CPU during
system power up.
This can be accomplished by placing external logic between the
VID[4:0] outputs of the processor and the voltage select inputs
of the DC/DC regulator. The System Power Good (SPWRGD)
signal can then be used as an input to the external logic to strap
the DC/DC regulator’s voltage select inputs to the desired state
until the processor’s VID[4:0] outputs have been initialized.
I
When SPWRGD is negated, the external logic drives the
selected strap value to the regulator’s D[4:0] inputs.
When SPWRGD is asserted, the external logic allows the
CPU VID[4:0] outputs to drive the regulator’s D[4:0] inputs.
Note:
The SPWRGD signal must only assert after all power good
signals (I/O, core, +5-V, etc.) are asserted.
I
For a minimum BF[2:0] boot strap option (see page 9), a
multiplexer and the SPWRGD signal can be used for this
purpose.
For a maximum BF[2:0] boot strap option (see page 9), a
multiplexer function is incorporated through the recommended
AND-gate solution discussed in "Subset of VID[4:0] Outputs
Used" on page 12.
In both cases, the SPWRGD signal, when equal to 0, forces the
VID[4:0] outputs of the external logic to a value equivalent to
the output state that the processor drives on its VID[4:0] pins
when SPWRGD transitions to a 1. Once RESET is negated,
BIOS is free to transition the processor core frequency and
voltage as needed.
Figure 5 on page 25 helps to illustrate the concept of
implementing a guaranteed CPU core voltage at power on.
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