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10
Dynamic Core Frequency and Core Voltage Control
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
Dynamic Core Frequency Control
For Microsoft operating systems, the BVC field of the EPM 16-
byte I/O block is accessed through an SMM handler.
I
To invoke a new processor core frequency, the SMM handler
initiates core voltage and frequency transitions by writing a
1 to the GSBC field in the EPMR and a non-zero value to the
SGTC.
This action initiates a special bus cycle to place the
processor into the EPM Stop Grant state and transitions the
CPU core voltage and frequency to the values specified in
the VIDO and IBF fields of the BVC field.
Note:
System-initiated inquire (snoop) cycles are not supported
and must be prevented by the BIOS or operating system
while in the EPM Stop Grant state.
I
BVC Field
Figure 3 on page 11 shows the format and Table 5 defines the
function of each bit of the BVC field located within the EPM 16-
byte I/O block.
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