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| 型號： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow?。考夹g平臺設計指南應用指南“ |
| 文件頁數(shù)： | 21/50頁 |
| 文件大?。?/td> | 957K |
| 代理商： | 24267A |
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Dynamic Core Frequency and Core Voltage Control
15
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
Dynamic Core Voltage Control
For Microsoft operating systems, the BVC field of the EPM 16-
byte I/O block is accessed through an SMM handler. To invoke a
new processor core voltage, the SMM handler initiates core
voltage and frequency transitions by writing a 1 to the GSBC
field in the EPMR and a non-zero value to the SGTC. This action
automatically places the processor into the EPM Stop Grant
state and transitions the CPU core voltage to the value
specified in the VIDO field of the BVC field.
Note:
System-initiated inquire (snoop) cycles are not supported
and must be prevented by the BIOS or operating system
while in the EPM Stop Grant state. This is typically
accomplished through the use of the ACPI-defined ARB_DIS
control bit, which turns off the PCI bus arbiter in the north
bridge.
The VID[4:0] outputs are determined by the value stored in the
VIDO field within the BVC field of the 16-byte I/O block during
AMD PowerNow! technology state transitions. For more
information on the format and definition of the BVC field, see
“BVC Field” on page 10.
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