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| 型號(hào)： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow！？技術(shù)平臺(tái)設(shè)計(jì)指南應(yīng)用指南“ |
| 文件頁數(shù)： | 13/50頁 |
| 文件大?。?/td> | 957K |
| 代理商： | 24267A |
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Dynamic Core Frequency and Core Voltage Control
7
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
Dynamic Core Frequency and Core Voltage Control
AMD-K6-2E+ and AMD-K6-IIIE+ processors enabled with
AMD PowerNow! technology support the ability to change the
bus frequency divisor and core voltage seamlessly during run
time. These features are implemented in conjunction with a
new clock control state—the EPM Stop Grant state.
To invoke an AMD PowerNow! technology state transition, the
desired settings for core voltage and processor frequency are
written to the Voltage ID Output (VIDO) and Internal BF
Divisor (IBF) fields of the BVC field. The EPM Stop Grant state
and state transition then occur automatically by writing a 1 to
the Generate Special Bus Cycle (GSBC) bit in the EPMR and a
non-zero value to the Stop Grant Time-out Counter (SGTC)
field.
For Microsoft operating systems, the EPMR register should be
accessed using an SMM handler. In these environments, the
SMM handler can initiate a special bus cycle for core voltage
and frequency transitions by writing a 1 to the GSBC field in the
EPMR and a non-zero value to the SGTC.
I
This action enables the processor to enter the EPM Stop
Grant State and transitions the CPU core voltage and
frequency to the values specified in the VIDO and IIBF
fields of the BVC field.
Once the SGTC period has expired, the EPM Stop Grant
state is exited and the AMD PowerNow! technology state
transition is completed.
I
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