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| 型號： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow??？技術(shù)平臺設(shè)計(jì)指南應(yīng)用指南“ |
| 文件頁數(shù)： | 45/50頁 |
| 文件大?。?/td> | 957K |
| 代理商： | 24267A |
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Appendix A—Frequently Asked Questions
39
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
Appendix A—Frequently Asked Questions
New Output Pins
Question:
What kind of output buffer do the new
AMD PowerNow! technology output pins have
Answer:
The new processor output pins have standard CMOS
“push-pull” driver buffers. All outputs are always driven.
Question:
Are the new AMD PowerNow! technology output pins
5-V-tolerant
Answer:
No. The new AMD PowerNow! technology output pins
adhere to the standard 3.3-V AMD-K6 family I/O voltage
specification.
Question:
What should be done for any AMD PowerNow!
technology output pin that is not used
Answer:
Unused AMD PowerNow! technology output pins
should be treated as NCs (no-connects).
AMD PowerNow! Technology State Transitions
Question:
Are there any design limitations to voltage or bus
frequency transitions
Answer:
Yes. System-initiated inquire (snoop) cycles are not
supported and must be prevented during AMD PowerNow!
technology transitions by setting the ARB_DIS bit in the north
bridge.
Question:
Is there a need to stop the CPU clock during state
transitions
Answer:
No. However, state transitions must be performed while
the processor is in the EPM Stop Grant State. The EPM Stop
Grant state is a low-power, clock-control state entered by
writing a non-zero value to the SGTC field for the purpose of
changing the processor core frequency and voltage.
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