參數(shù)資料
型號: 28F008S
廠商: Intel Corp.
英文描述: 8-MBit (1 MBit x 8) FLASHFILE Memory(8-M位 (1 M位 x 8)閃速存儲器)
中文描述: 8兆(1兆比特× 8)FLASHFILE內(nèi)存(8米位(1米位× 8)閃速存儲器)
文件頁數(shù): 17/28頁
文件大?。?/td> 347K
代理商: 28F008S
28F008SA-L
V
CC
, V
PP
, RP
Y
Transitions and the
Command/Status Registers
Byte write and block erase completion are not guar-
anteed if V
PP
drops below V
PPH
. If the V
PP
Status bit
of the Status Register (SR.3) is set to ‘‘1’’, a Clear
Status Register command MUST be issued before
further byte write/block erase attempts are allowed
by the WSM. Otherwise, the Byte Write (SR.4) or
Erase (SR.5) Status bits of the Status Register will
be set to ‘‘1’’s if error is detected. RP
Y
transitions to
V
IL
during byte write and block erase also abort the
operations. Data is partially altered in either case,
and the command sequence must be repeated after
normal operation is restored. Device poweroff, or
RP
Y
transitions to V
IL
, clear the Status Register to
initial value 10000 for the upper 5 bits.
The Command User Interface latches commands as
issued by system software and is not altered by V
PP
or CE
Y
transitions or WSM actions. Its state upon
powerup, after exit from deep powerdown or after
V
CC
transitions below V
LKO
, is Read Array Mode.
After byte write or block erase is complete, even
after V
PP
transitions down to V
PPL
, the Command
User Interface must be reset to Read Array mode via
the Read Array command if access to the memory
array is desired.
Power Up/Down Protection
The 28F008SA-L is designed to offer protection
against accidental block erasure or byte writing dur-
ing
power
transitions.
28F008SA-L is indifferent as to which power supply,
V
PP
or V
CC
, powers up first. Power supply sequenc-
ing
is
not
required.
Internal
Upon
power-up,
the
circuitry
in
the
28F008SA-L ensures that the Command User Inter-
face is reset to the Read Array mode on power up.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active. Since both WE
Y
and CE
Y
must be low for a
command write, driving either to V
IH
will inhibit
writes. The Command User Interface architecture
provides an added level of protection since altera-
tion of memory contents only occurs after success-
ful completion of the two-step command sequences.
Finally, the device is disabled until RP
Y
is brought to
V
IH
, regardless of the state of its control inputs. This
provides an additional level of memory protection.
Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases us-
able battery life, because the 28F008SA-L does not
consume any power to retain code or data when the
system is off.
In addition, the 28F008SA-L’s deep powerdown
mode ensures extremely low power dissipation even
when system power is applied. For example, porta-
ble PCs and other power sensitive applications, us-
ing an array of 28F008SA-Ls for solid-state storage,
can lower RP
Y
to V
IL
in standby or sleep modes,
producing negligable power consumption. If access
to the 28F008SA-L is again needed, the part can
again be read, following the t
PHQV
and t
PHWL
wake-
up cycles required after RP
Y
is first raised back to
V
IH
. See AC CharacteristicsDRead-Only and Write
Operations and Figures 10 and 11 for more informa-
tion.
17
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