參數(shù)資料
型號: 28F008S
廠商: Intel Corp.
英文描述: 8-MBit (1 MBit x 8) FLASHFILE Memory(8-M位 (1 M位 x 8)閃速存儲器)
中文描述: 8兆(1兆比特× 8)FLASHFILE內(nèi)存(8米位(1米位× 8)閃速存儲器)
文件頁數(shù): 9/28頁
文件大?。?/td> 347K
代理商: 28F008S
28F008SA-L
Data Protection
Depending on the application, the system designer
may choose to make the V
PP
power supply switcha-
ble (available only when memory byte writes/block
erases are required) or hardwired to V
PPH
. When
V
PP
e
V
PPL
, memory contents cannot be altered.
The 28F008SA-L Command User Interface architec-
ture provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V
PP
. Additionally, all functions are dis-
abled whenever V
CC
is below the write lockout volt-
age V
LKO
, or when RP
Y
is at V
IL
. The 28F008SA-L
accommodates either design practice and encour-
ages optimization of the processor-memory inter-
face.
The two-step byte write/block erase Command User
Interface write sequence provides additional soft-
ware write protection.
BUS OPERATION
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
Read
The 28F008SA-L has three read modes. The memo-
ry can be read from any of its blocks, and informa-
tion can be read from the Intelligent Identifier or
Status Register. V
PP
can be at either V
PPL
or V
PPH
.
The first task is to write the appropriate read mode
command to the Command User Interface (array, In-
telligent
Identifier,
or
28F008SA-L automatically resets to Read Array
mode upon initial device powerup or after exit from
deep powerdown. The 28F008SA-L has four control
pins, two of which must be logically active to obtain
data at the outputs. Chip Enable (CE
Y
) is the device
selection control, and when active enables the se-
lected memory device. Output Enable (OE
Y
) is the
data input/output (DQ
0
–DQ
7
) direction control, and
when active drives data from the selected memory
onto the I/O bus. RP
Y
and WE
Y
must also be at
V
IH
. Figure 10 illustrates read bus cycle waveforms.
Status
Register).
The
Output Disable
With OE
Y
at a logic-high level (V
IH
), the device out-
puts are disabled. Output pins (DQ
0
–DQ
7
) are
placed in a high-impedance state.
Standby
CE
Y
28F008SA-L in standby mode. Standby operation
disables much of the 28F008SA-L’s circuitry and
substantially reduces device power consumption.
The outputs (DQ
0
–DQ
7
) are placed in a high-impe-
dence state independent of the status of OE
Y
. If the
28F008SA-L is deselected during block erase or
byte write, the device will continue functioning and
consuming normal active power until the operation
completes.
at
a
logic-high
level
(V
IH
)
places
the
Table 2. Bus Operations
Mode
Notes
RP
Y
CE
Y
OE
Y
WE
Y
A
0
V
PP
DQ
0–7
RY/BY
Y
Read
1, 2, 3
V
IH
V
IL
V
IL
V
IH
X
X
D
OUT
X
Output Disable
1, 2, 3
V
IH
V
IL
V
IH
V
IH
X
X
High Z
X
Standby
1, 2, 3
V
IH
V
IH
X
X
X
X
High Z
X
Deep PowerDown
1, 2
V
IL
X
X
X
X
X
High Z
V
OH
Intelligent Identifier (Mfr)
1, 2
V
IH
V
IL
V
IL
V
IH
V
IL
X
89H
V
OH
Intelligent Identifier (Device)
1, 2
V
IH
V
IL
V
IL
V
IH
V
IH
X
A1H
V
OH
Write
1, 2, 3, 4, 5
V
IH
V
IL
V
IH
V
IL
X
X
D
IN
X
NOTES:
1. Refer to DC Characteristics. When V
PP
e
V
PPL
, memory contents can be read but not written or erased.
2. X can be V
IL
or V
IH
for control pins and addresses, and V
PPL
or V
PPH
for V
PP
. See DC Characteristics for V
PPL
and V
PPH
voltages.
3. RY/BY
Y
is V
OL
when the Write State Machine is executing internal block erase or byte write algorithms. It is V
OH
when
the WSM is not busy, in Erase Suspend mode or deep powerdown mode.
4. Command writes involving block erase or byte write are only successfully executed when V
PP
e
V
PPH
.
5. Refer to Table 3 for valid D
IN
during a write operation.
9
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