參數(shù)資料
型號: 28F008S
廠商: Intel Corp.
英文描述: 8-MBit (1 MBit x 8) FLASHFILE Memory(8-M位 (1 M位 x 8)閃速存儲器)
中文描述: 8兆(1兆比特× 8)FLASHFILE內(nèi)存(8米位(1米位× 8)閃速存儲器)
文件頁數(shù): 21/28頁
文件大小: 347K
代理商: 28F008S
28F008SA-L
DC CHARACTERISTICS
(Continued) V
CC
e
5.0V
g
10%
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
V
PPH
V
PP
during Erase/Write
Operations
11.4
12.0
12.6
V
V
LKO
V
CC
Erase/Write Lock
Voltage
2.0
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
CC
e
5.0V, V
PP
e
12.0V, T
e
25
§
C. These currents
are valid for all product versions (packages and speeds).
2. I
CCES
is specified with the device deselected. If the 28F008SA-L is read while in Erase Suspend Mode, current draw is
the sum of I
CCES
and I
CCR
.
3. Includes RY/BY
Y
.
4. Block Erases/Byte Writes are inhibited when V
PP
e
V
PPL
and not guaranteed in the range between V
PPH
and V
PPL
.
AC INPUT/OUTPUT REFERENCE WAVEFORM
290435–7
AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0V for a Logic ‘‘0’’. Input timing
begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%)
k
10 ns.
AC TESTING LOAD CIRCUIT
(2)
C
L
e
50 pF
C
L
Includes Jig
Capacitance
R
L
e
3.3 k
X
290435–8
AC CHARACTERISTICSDRead-Only Operations
(1)
V
CC
e
3.3V
g
0.3V, 5.0V
g
10%
Versions
28F008SA-150
Unit
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
RC
Read Cycle Time
150
ns
t
AVQV
t
ACC
Address to Output Delay
150
ns
t
ELQV
t
CE
CE
Y
to Output Delay
2
150
ns
t
PHQV
t
PWH
RP
Y
High to Output Delay
600
ns
t
GLQV
t
OE
OE
Y
to Output Delay
2
75
ns
t
ELQX
t
LZ
CE
Y
to Output Low Z
3
0
ns
t
EHQZ
t
HZ
CE
Y
High to Output High Z
3
55
ns
t
GLQX
t
OLZ
OE
Y
to Output Low Z
3
0
ns
t
GHQZ
t
DF
OE
Y
High to Output High Z
3
30
ns
t
OH
Output Hold from Addresses, CE
Y
or OE
Y
Change, Whichever is First
3
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE
Y
may be delayed up to t
CE
–t
OE
after the falling edge of CE
Y
without impact on t
CE
.
3. Sampled, not 100% tested.
21
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