參數(shù)資料
型號: 28F008S
廠商: Intel Corp.
英文描述: 8-MBit (1 MBit x 8) FLASHFILE Memory(8-M位 (1 M位 x 8)閃速存儲器)
中文描述: 8兆(1兆比特× 8)FLASHFILE內(nèi)存(8米位(1米位× 8)閃速存儲器)
文件頁數(shù): 26/28頁
文件大小: 347K
代理商: 28F008S
28F008SA-L
ALTERNATIVE CE
Y
-CONTROLLED WRITES
V
CC
e
3.3V
g
0.3V, 5.0V
g
10%
Versions
28F008SA-L200
Unit
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
WC
Write Cycle Time
200
ns
t
PHEL
t
PS
RP
Y
High Recovery to CE
Y
Going Low
2
1
m
s
t
WLEL
t
WS
WE
Y
Setup to CE
Y
Going Low
0
ns
t
ELEH
t
CP
CE
Y
Pulse Width
70
ns
t
VPEH
t
VPS
V
PP
Setup to CE
Y
Going High
Address Setup to CE
Y
Going High
2
100
ns
t
AVEH
t
AS
3
60
ns
t
DVEH
t
DS
Data Setup to CE
Y
Going High
4
60
ns
t
EHDX
t
DH
Data Hold from CE
Y
High
5
ns
t
EHAX
t
AH
Address Hold from CE
Y
High
5
ns
t
EHWH
t
WH
WE
Y
Hold from CE
Y
High
0
ns
t
EHEL
t
EPH
CE
Y
Pulse Width High
25
ns
t
EHRL
CE
Y
High to RY/BY
Y
Going Low
100
ns
t
EHQV1
Duration of Byte Write Operation
5
6
m
s
t
EHQV2
Duration of Block Erase Operation
5
0.3
sec
t
EHGL
Write Recovery before Read
0
m
s
t
QVVL
t
VPH
V
PP
Hold from Valid SRD, RY/BY
Y
High
2, 5
0
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE
Y
and WE
Y
. In systems where
CE
Y
defines the write pulsewidth (within a longer WE
Y
timing waveform), all setup, hold and inactive WE
Y
times should
be measured relative to the CE
Y
waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A
IN
for byte write or block erasure.
4. Refer to Table 3 for valid D
IN
for byte write or block erasure.
5. Byte write and block erase durations are measured to completion (SR.7
e
1, RY/BY
Y
e
V
OH
). V
PP
should be held at
V
PPH
until determination of byte write/block erase success (SR.3/4/5
e
0)
26
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