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參數(shù)資料
| 型號： | 28F020 |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Bulk Erase Flash Memory(5V 整體擦寫閃速存儲器) |
| 中文描述： | 5伏體擦除閃存（5V的整體擦寫閃速存儲器） |
| 文件頁數(shù)： | 11/47頁 |
| 文件大小： | 758K |
| 代理商： | 28F020 |
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E
2.2.1.3
28F010/28F020
11
Standby
With CE# at a logic-high level, the standby
operation disables most of the 28F010 and
28F020’s circuitry and substantially reduces device
power consumption. The outputs are placed in a
high-impedance state, independent of the OE#
signal. If the 28F010 and 28F020 are deselected
during erasure, programming, or program/erase
verification, the device draws active current until the
operation is terminated.
2.2.1.4
Intelligent Identifier Operation
The intelligent identifier operation outputs the
manufacturer code (89H) and device code (B4H for
28F010, BDH for 28F020). Programming equipment
automatically matches the device with its proper
erase and programming algorithms.
With CE# and OE# at a logic low level, raising A
9
to
high voltage V
ID
(see
DC Characteristics
) activates
the operation. Data read from locations 0000H and
0001H represent the manufacturer's code and the
device code, respectively.
The manufacturer and device codes can also be
read via the command register, for instances where
the
28F010
and
28F020
reprogrammed in the target system. Following a
write of 90H to the command register, a read from
address location 0000H outputs the manufacturer
code (89H). A read from address 0001H outputs the
device code (B4H for 28F010, BDH for 28F020).
are
erased
and
2.2.1.5
Write
Device erasure and programming are accomplished
via the command register, when high voltage is
applied to the V
PP
pin. The contents of the register
serve as input to the internal state machine. The
state machine outputs dictate the function of the
device.
The command register itself does not occupy an
addressable memory location. The register is a
latch used to store the command, along with
address and data information needed to execute
the command.
The command register is written by bringing WE# to
a logic-low level (V
IL
), while CE# is low. Addresses
are latched on the falling edge of WE#, while data is
latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
Refer to
AC Characteristics
—Write/Erase/Program
Only Operations
and the erase/programming
waveforms for specific timing parameters.
2.2.2
COMMAND DEFINITIONS
When low voltage is applied to the V
PP
pin, the
contents of the command register default to 00H,
enabling read-only operations.
Placing high voltage on the V
PP
pin enables
read/write operations. Device operations are
selected by writing specific data patterns into the
command
register.
Table 3
28F010/28F020 register commands.
defines
these
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