參數(shù)資料
型號(hào): 28F128
廠商: Intel Corp.
英文描述: 3 Volt Intel StrataFlash Memory
中文描述: 3伏特英特爾StrataFlash存儲(chǔ)器
文件頁數(shù): 1/58頁
文件大小: 380K
代理商: 28F128
3 Volt Intel
StrataFlash
Memory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16)
Preliminary
Datasheet
Product Features
Capitalizing on Intel’s 0.25 μ generation two-bit-per-cell technology, second generation Intel
StrataFlash
memory products provide 2X the bits in 1X the space, with new features for mainstream
performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring
reliable, two-bit-per-cell storage technology to the flash market segment.
Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX
technology as Intel
s one-bit-per-cell products, Intel StrataFlash
memory
devices take advantage of over one billion units of manufacturing experience since 1987. As a
result, Intel StrataFlash components are ideal for code and data applications where high density and low
cost are required. Examples include networking, telecommunications, digital set top boxes, audio
recording, and digital imaging.
By applying FlashFile
memory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation
Intel StrataFlash memory (28F640J5 and 28F320J5) devices.
Intel StrataFlash memory components deliver a new generation of forward-compatible software support.
By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel
0.25 micron ETOX
VI process technology, Intel StrataFlash memory provides
the highest levels of quality and reliability.
I
High-Density Symmetrically-Blocked
Architecture
128 128-Kbyte Erase Blocks (128 M)
6
4 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
I
High Performance Interface Asynchronous
Page Mode Reads
110/25 ns Read Access Time (32 M)
120/25 ns Read Access Time (64 M)
150/25 ns Read Access Time (128 M)
I
2.7 V
3.6 V V
CC
Operation
I
128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP Cells
I
Enhanced Data Protection Features
Absolute Protection with V
PEN
= GND
Flexible Block Locking
Block Erase/Program Lockout during
Power Transitions
I
Packaging
56-Lead TSOP Package
64-Ball Intel
Easy BGA Package
I
Cross-Compatible Command Support Intel
Basic Command Set
Common Flash Interface
Scalable Command Set
I
32-Byte Write Buffer
6 μs per Byte Effective Programming
Time
I
12.8M Total Min. Erase Cycles (128 Mbit)
6.4M Total Min. Erase Cycles (64 Mbit)
3.2M Total Min. Erase Cycles (32 Mbit)
100K Minimum Erase Cycles per Block
I
Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
Program Suspend to Read
I
0.25 μ Intel
StrataFlash
Memory
Technology
Order Number: 290667-008
April 2001
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
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