參數(shù)資料
型號(hào)： 28F020
廠商： Intel Corp.
英文描述： 5 V Bulk Erase Flash Memory(5V 整體擦寫(xiě)閃速存儲(chǔ)器)
中文描述： 5伏體擦除閃存（5V的整體擦寫(xiě)閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 13/47頁(yè)
文件大?。?/td> 758K
代理商： 28F020
E
The 28F010 and 28F020 contain an intelligent
identifier operation to supplement traditional PROM-
programming methodology. The operation is
initiated by writing 90H into the command register.
Following the command Write, a read cycle from
address 0000H retrieves the manufacturer code of
89H. A read cycle from address 0001H returns the
device code of (B4H for 28F010, BDH for 28F020).
To terminate the operation, it is necessary to write
another valid command into the register.
28F010/28F020
13
2.2.2.3
Set-Up Erase/Erase Commands
Set-Up Erase is a command-only operation that
stages the device for electrical erasure of all bytes
in the array. The set-up erase operation is
performed by writing 20H to the command register.
To commence chip-erasure, the Erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
WE# pulse and terminates with the rising edge of
the next WE# pulse (i.e., Erase Verify command).
This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, chip-erasure can only
occur when high voltage is applied to the pin. In the
absence of this high voltage, memory contents are
protected
against
erasure.
Characteristics
—Write/Erase/Program Only Oper-
ations
and
waveforms
parameters.
Refer
to
AC
for
specific
timing
2.2.2.4
Erase Verify Command
The Erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing A0H into the command register. The
address for the byte to be verified must be supplied
as it is latched on the falling edge of the WE# pulse.
The register write terminates the erase operation
with the rising edge of its WE# pulse.
The 5 Volt Bulk Erase applies an internally-
generated margin voltage to the addressed byte.
Reading FFH from the addressed byte indicates
that all bits in the byte are erased.
The Erase Verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer Section
2.2.2.3,
Set-Up
Erase/Erase
Verification then resumes from the address of the
last-verified byte. Once all bytes in the array have
been verified, the erase step is complete. The
device can be programmed. At this point, the verify
operation is terminated by writing a valid command
(e.g., Program Set-Up) to the command register.
Figure 5,
the
28F010/28F020
Algorithm
flowchart, illustrates how commands and
bus operations are combined to perform electrical
erasure of the 28F010 and 28F020. Refer to
AC
Characteristics—Write/Erase/Program Only Oper-
ations
and
waveforms
parameters.
Commands.
)
Quick-Erase
for
specific
timing
2.2.2.5
Set-Up Program/Program
Commands
Set-up program is a command-only operation that
stages the device for byte programming. Writing
40H into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next WE# pulse causes a transition to an active
programming operation. Addresses are internally
latched on the falling edge of the WE# pulse. Data
is internally latched on the rising edge of the WE#
pulse. The rising edge of WE# also begins the
programming
operation.
operation terminates with the next rising edge of
WE#, used to write the Program Verify command.
Refer to
AC Characteristics—Write/Erase/Program
Only Operations
and Waveforms for specific timing
parameters.
The
programming
2.2.2.6
Program Verify Command
The 5 Volt Bulk Erase is programmed on a byte-by-
byte
basis.
Byte
programming
sequentially
or
at
random.
programming operation, the byte just programmed
must be verified.
may
occur
each
Following
The program verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the
rising edge of its WE# pulse. The program verify
operation stages the device for verification of the
byte last programmed. No new address information
is latched.
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