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參數(shù)資料
| 型號(hào)： | 30044-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible with MMX Support 32-Bit Geode GXm Processor(低功耗集成兼容X86帶有MMX的32位 Geode GXm技術(shù)處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁(yè)數(shù)： | 109/244頁(yè) |
| 文件大?。?/td> | 4496K |
| 代理商： | 30044-23 |
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Revision 3.1
109
www.national.com
Integrated Functions (
Continued
)
G
25:23
MEMHDCTL
Control High Drive/Slew Control:
Controls the high drive and slew rate of the memory control sig-
nals (CASA#, CASB#, RASA#, RASB#, CKEA, CKEB, WEA#, WEA#, DQM[7:0], and CS[3:0]#):
000 = Tristate
001 = Smallest drive strength
010 -110 = Represents gradual drive strength increase
111 = Highest drive strength
Reserved:
Set to 0.
Reserved:
Must be set to 0. Wait state on the X-Bus x_data during read cycles - for debug only.
SDRAM Clock Ratio:
Selects SDRAM clock ratio:
000 = Reserved
001 = ÷ 2
010 = ÷ 2.5
011 = ÷ 3 (Default)
Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.
Start SDCLK:
Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of
this register): 0 = Clear; 1 = Enable.
This bit should be cleared every time before a one is written to it in order to start SDCLK or to change
the shift value.
Refresh Interval:
This field determines the number of processor core clocks multiplied by 64 between
refresh cycles to the DRAM. By default, the refresh interval is 00h. This implies that refresh is turned
off by default.
Refresh Staggering:
This field determines number of clocks between REF commands to different
banks during refresh cycles:
00 = 0 SDRAM clocks
01 = 1 SDRAM clocks (Default)
Staggering is used to help reduce power spikes during refresh. When only DIMM0 is installed and it
has only one DIMM bank, then this field must be set to 00.
Two Clock Address Setup:
Assert memory address for one extra clock before CS# is asserted:
0 = Disable; 1 = Enable.
This can be used to compensate for address setup at high frequencies.
Test Refresh:
This bit, when set high, generates a refresh request. This bit is only used for testing
purposes.
X-Bus Round Robin:
When enabled, processor requests are arbitrated at the same priority level than
graphics pipeline requests and non-critical display controller requests. When disabled, processor
requests are arbitrated at a higher priority level. High priority display controller requests always have
the highest arbitration priority: 0 = Enable; 1 = Disable.
VGA Wrap Enable:
Allow memory wrapping into the VGA memory address space from A0000h to
BFFFFh: 0 = Disable; 1 = Enable.
Reserved:
Set to 0.
Program SDRAM:
When this bit is set the memory controller will program the SDRAM MRS register
using LTMODE in MC_SYNC_TIM1.
This bit should be cleared every time before a one is written to it in order to program the SDRAM.
22
21
RSVD
RSVD
20:18
SDCLKRATE
100 = ÷ 3.5
101 = ÷ 4
110 = ÷ 4.5
111 = ÷ 5
17
SDCLKSTRT
16:8
RFSHRATE
7:6
RFSHSTAG
10 = 2 SDRAM clocks
11 = 4 SDRAM clocks
5
2CLKADDR
4
RFSHTST
3
XBUSARB
2
VGAWRP
1
0
RSVD
SDRAMPRG
GX_BASE+8404h-8407h
MC_MEM_CNTRL2 (R/W)
Default Value = 00000801h
31:18
17:16
RSVD
Reserved:
Set to 0.
SDCLK Rising Delay:
Controls the delay between the core clock and the rising edge of SDCLK dur-
ing all modes. (Set by BIOS.)
SDCLK Falling Delay:
Controls the delay between the core clock and the falling edge of SDCLK dur-
ing 2.5 and 3.5 clock modes. (Set by BIOS.)
SDCLK High Drive/Slew Control:
Controls the high drive and slew rate of SDCLK[3:0] and
SDCLK_OUT.
000 = Highest drive strength. (No braking applied in the pads)
001 = Smallest drive strength
010 -110 = Represent gradual drive strength increase
111 = Highest drive strength
Mask SDCLK_OUT:
0 = Not masked; 1 = Mask.
SDCLKRISE
15:14
SDCLKFALL
13:11
SDCLKHDCTL
10
SDCLKOMSK
Table 4-16. Memory Controller Registers (Continued)
Bit
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 30046-23 | Low Power Integrated x86-Compatible 32-Bit Geode GXLV Processor(低功耗集成兼容X86的32位 Geode GXLV技術(shù)處理器) |
| 300471U | Radial, -55dotc, long life wsitching-power |
| 300CNQ | SCHOTTKY RECTIFIER |
| 300CNQ035 | SCHOTTKY RECTIFIER |
| 300CNQ040 | SCHOTTKY RECTIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3004430 | 功能描述:DIN導(dǎo)軌式接線端子 UK 5-MTK RoHS:否 制造商:Phoenix Contact 類型:Feed Through Modular Terminal Block 位置/觸點(diǎn)數(shù)量:1 線規(guī)量程:26-14 電流額定值:5 A, 15 A 電壓額定值:300 V, 600 V 安裝風(fēng)格: 端接類型:Push-In |
| 30044-44L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 70MM |
| 3004472 | 制造商:Phoenix Contact 功能描述:UK 5-HESI (5X20) |
| 300448 | 功能描述:手工工具 RETAINING PIN RoHS:否 制造商:Molex 產(chǎn)品:Extraction Tools 類型: 描述/功能:Extraction tool |
| 300449 | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:HAND TOOL ASSEMBLY |
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