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2
Revision 3.1
G
Features
General Features
Packaged in:
— 352-Terminal Ball Grid Array (BGA) or
— 320-Pin Staggered Pin Grid Array (SPGA)
0.35-micron four layer metal CMOS process
Split rail design (3.3V I/O and 2.9V core)
32-Bit x86 Processor
Supports the MMX instruction set extension for the
acceleration of multimedia applications
Speeds offered up to 266 MHz
16 KB unified L1 cache
Integrated Floating Point Unit (FPU)
Re-entrant System Management Mode (SMM)
enhanced for VSA
PCI Controller
Fixed, rotating, hybrid, or ping-pong arbitration
Supports up to three PCI bus masters
Synchronous CPU and PCI bus clock frequency
Supports concurrency between PCI master and L1
cache
Power Management
Designed to support CS5530 power management
architecture
CPU only Suspend or full 3V Suspend supported:
— Clocks to CPU core stopped for CPU Suspend
— All on-chip clocks stopped for 3V Suspend
— Suspend refresh supported for 3V Suspend
Virtual Systems Architecture Technology
Architecture allows OS independent (software) virtual-
ization of hardware functions
Provides compatible high performance legacy VGA
core functionality
Note:
GUI (Graphical User Interface) graphics accel-
eration is pure hardware.
Provides 16-bit XpressAUDIO subsystem
2D Graphics Accelerator
Graphics pipeline performance significantly increased
over previous generations by pipelining burst
reads/writes
Accelerates BitBLTs, line draw, text
Supports all 256 raster operations
Supports transparent BLTs
Runs at core clock frequency
Full VGA and VESA mode support
Special "Driver level” instructions utilize internal
scratchpad for enhanced performance
Display Controller
Video Generator (VG) improves memory efficiency for
display refresh with SDRAM
Supports a separate MPEG1 video buffer and data
path to enable video acceleration in the CS5530
Internal palette RAM for use with the CS5530
Direct interface to CS5530 for CRT and TFT flat panel
support which eliminates need for external RAMDAC
Hardware frame buffer compressor/decompressor
Hardware cursor
Supports up to 1280x1024x8 bpp and 1024x768x16
bpp
XpressRAM Subsystem
Memory control/interface directly from CPU
64-Bit wide memory bus
Support for:
— Two 168-pin unbuffered DIMMs
— Up to 16 open banks simultaneously
— Single or 16-byte reads (burst length of two)