- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358620 > 30044-23 (NATIONAL SEMICONDUCTOR CORP) Low Power Integrated x86-Compatible with MMX Support 32-Bit Geode GXm Processor(低功耗集成兼容X86帶有MMX的32位 Geode GXm技術(shù)處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | 30044-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible with MMX Support 32-Bit Geode GXm Processor(低功耗集成兼容X86帶有MMX的32位 Geode GXm技術(shù)處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁數(shù)： | 9/244頁 |
| 文件大?。?/td> | 4496K |
| 代理商： | 30044-23 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁
Revision 3.1
9
www.national.com
Architecture Overview (
Continued
)
G
1.2
The FPU (Floating Point Unit) interfaces to the integer unit
and the cache unit through a 64-bit bus. The FPU is x87-
instruction-set compatible and adheres to the IEEE-754
standard. Because almost all applications that contain
FPU instructions also contain integer instructions, the
GXm processor’s FPU achieves high performance by
completing integer and FPU operations in parallel.
FLOATING POINT UNIT
FPU instructions are dispatched to the pipeline within the
integer unit. The address calculation stage of the pipeline
checks
for
memory
management
accesses memory operands for use by the FPU. Once the
instructions and operands have been provided to the FPU,
the FPU completes instruction execution independently of
the integer unit.
exceptions
and
1.3
The 16 KB write-back unified cache is a data/instruction
cache and is configured as four-way set associative. The
cache stores up to 16 KB of code and data in 1024 cache
lines.
WRITE-BACK CACHE UNIT
The GXm processor provides the ability to allocate a por-
tion of the L1 cache as a scratchpad, which is used to
accelerate the Virtual Systems Architecture algorithms as
well as for some graphics operations.
1.4
The memory management unit (MMU) translates the lin-
ear address supplied by the integer unit into a physical
address to be used by the cache unit and the internal bus
interface unit. Memory management procedures are x86-
compatible, adhering to standard paging mechanisms.
MEMORY MANAGEMENT UNIT
The MMU also contains a load/store unit that is responsi-
ble for scheduling cache and external memory accesses.
The
load/store
unit
incorporates
enhancing features:
two
performance-
Load-store reordering
that gives priority to memory
reads required by the integer unit over writes to
external memory.
Memory-read bypassing
that eliminates unnecessary
memory reads by using valid data from the execution
unit.
1.4.1
The internal bus interface unit provides a bridge from the
GXm processor to the integrated system functions (i.e.,
memory subsystem, display controller, graphics pipeline)
and the PCI bus interface.
Internal Bus Interface Unit
When external memory access is required, the physical
address is calculated by the memory management unit
and then passed to the internal bus interface unit, which
translates the cycle to an X-Bus cycle (the X-Bus is a
National Semiconductor proprietary internal bus which
provides a common interface for all of the system mod-
ules). The X-Bus memory cycle now is arbitrated between
other pending X-Bus memory requests to the SDRAM
controller before completing.
In addition, the internal bus interface unit provides config-
uration control for up to 20 different regions within system
memory with separate controls for read access, write
access, cacheability, and PCI access.
1.5
The GXm processor integrates the following functions tra-
ditionally implemented using external devices:
INTEGRATED FUNCTIONS
High-performance 2D graphics accelerator
Separate CRT and TFT data paths from the display
controller
SDRAM memory controller
PCI bridge
The processor has also been enhanced to support
National Semiconductor’s proprietary Virtual System
Architecture (VSA) implementation.
The GXm processor implements a Unified Memory Archi-
tecture (UMA). By using National Semiconductor’s Dis-
play Compression Technology (DCT), the performance
degradation inherent in traditional UMA systems is elimi-
nated.
1.5.1
The graphics accelerator is a full-featured GUI (Graphical
User Interface) accelerator. The graphics pipeline imple-
ments a bitBLT engine for frame buffer bitBLTs and rect-
angular fills. Additional instructions in the integer unit may
be processed, as the bitBLT engine assists the CPU in the
bitBLT operations that take place between system mem-
ory and the frame buffer. This combination of hardware
and software is used by the display driver to provide very
fast transfers in both directions between system memory
and the frame buffer. The bitBLT engine also draws ran-
domly-oriented vectors, and scanlines for polygon fill. All
of the pipeline operations described in the following list
can be applied to any bitBLT operation.
Graphics Accelerator
Pattern Memory.
Render with 8x8 dither, 8x8 mono-
chrome, or 8x1 color pattern.
Color Expansion.
Expand monochrome bitmaps to
full-depth 8- or 16-bit colors.
Transparency.
Suppresses drawing of background
pixels for transparent text.
Raster Operations.
Boolean operation combines
source, destination, and pattern bitmaps.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 30046-23 | Low Power Integrated x86-Compatible 32-Bit Geode GXLV Processor(低功耗集成兼容X86的32位 Geode GXLV技術(shù)處理器) |
| 300471U | Radial, -55dotc, long life wsitching-power |
| 300CNQ | SCHOTTKY RECTIFIER |
| 300CNQ035 | SCHOTTKY RECTIFIER |
| 300CNQ040 | SCHOTTKY RECTIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3004430 | 功能描述:DIN導(dǎo)軌式接線端子 UK 5-MTK RoHS:否 制造商:Phoenix Contact 類型:Feed Through Modular Terminal Block 位置/觸點(diǎn)數(shù)量:1 線規(guī)量程:26-14 電流額定值:5 A, 15 A 電壓額定值:300 V, 600 V 安裝風(fēng)格: 端接類型:Push-In |
| 30044-44L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 70MM |
| 3004472 | 制造商:Phoenix Contact 功能描述:UK 5-HESI (5X20) |
| 300448 | 功能描述:手工工具 RETAINING PIN RoHS:否 制造商:Molex 產(chǎn)品:Extraction Tools 類型: 描述/功能:Extraction tool |
| 300449 | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:HAND TOOL ASSEMBLY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。