參數(shù)資料
型號(hào): 30044-23
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: Low Power Integrated x86-Compatible with MMX Support 32-Bit Geode GXm Processor(低功耗集成兼容X86帶有MMX的32位 Geode GXm技術(shù)處理器)
中文描述: 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320
封裝: SPGA-320
文件頁(yè)數(shù): 167/244頁(yè)
文件大?。?/td> 4496K
代理商: 30044-23
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)當(dāng)前第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)
Revision 3.1
167
www.national.com
Virtual Subsystem Architecture (
Continued
)
G
CPU to VGA memory are broken down into multiple byte
accesses by the sequencer. For example, a word write to
A0000h (in a VGA graphics mode) is processed as if it
were two-byte write operations to A0000h and A0001h.
5.1.1.3
When a VGA card sees an address on the host bus, bits
[31:15] determine whether the transaction is for the VGA.
Depending
on
the
mode,
000B{0XXX}XXX, or 000B{1XXX}XXXX can decode into
VGA space. If the access is for the VGA, bits [15:0] pro-
vide the DWORD address into the frame buffer (however,
see odd/even and Chain 4 modes, below). Thus, each
byte address on the host bus addresses a DWORD in
VGA memory.
Address Mapping
addresses
000AXXXX,
On a write transaction, the byte enables are normally
driven from the sequencer’s MapMask register. The VGA
has two other write address mappings that modify this
behavior. In odd/even (Chain 2) write mode, bit 0 of the
address is used to enable bytes 0 and 2 (if zero) or bytes
1 and 3 (if one). In addition, the address presented to the
frame buffer has bit 0 replaced with the PageBit field of
the Miscellaneous Output register. Chain 4 write mode is
similar; only one of the four byte enables is asserted,
based on bits [1:0] of the address, and bits [1:0] of the
frame buffer address are set to zero. In each of these
modes, the MapMask enables are logically ANDed into
the enables that result from the address.
5.2
The GXm processor provides VGA compatibility through a
mixture of hardware and software. The processor core
contains SMI generation hardware for VGA memory write
operations. The bus controller contains SMI generation
hardware for VGA I/O read and write operations. The
graphics pipeline contains hardware to detect and pro-
cess reads and writes to VGA memory. VGA memory is
partitioned from system memory.
GXM VIRTUAL VGA
5.2.1
The graphics controller contains several elements that
convert between host data and frame buffer data.
Datapath Elements
The rotator simply rotates the byte written from the host
by 0 to 7 bits to the right, based on the RotateCount field
of the DataRotate register. It has no effect in the read
path.
The display latch is a 32-bit register that is loaded on
every read access to the frame buffer. All 32 bits of the
frame buffer DWORDs are loaded into the latch.
The
write-mode unit
converts a byte from the host into a
32-bit value. A VGA has four write modes:
Write Mode 0:
- Bit n of byte b comes from one of two places,
depending on bit b of the EnableSetReset register. If
that bit is zero, it comes from bit n of the host data. If
that bit is one, it comes from bit b of the SetReset
register. This mode allows the programmer to set
some planes from the host data and the others from
SetReset.
Write Mode 1:
- All 32 bits come directly out of the display latch; the
host data is ignored. This mode is used for screen-
to-screen copies.
Write Mode 2:
- Bit n of byte b comes from bit b of the host data; that
is, the four LSBs of the host data are each replicated
through a byte of the result. In conjunction with the
BitMask register, this mode allows the programmer
to directly write a 4-bit color to one or more pixels.
Write Mode 3:
- Bit n of byte b comes from bit b of the SetReset
register. The host data is ANDed with the BitMask
register to provide the bit mask for the write (see
below).
The
read mode unit
converts a 32-bit value from the
frame buffer into a byte. A VGA has two read modes:
Read Mode 0:
- One of the four bytes from the frame buffer is
returned, based on the value of the ReadMapSelect
register. In Chain 4 mode, bits [1:0] of the read
address select a plane. In odd/even read mode, bit 0
of the read address replaces bit 0 of ReadMapSe-
lect.
Read Mode 1:
- Bit n of the result is set to 1 if bit n in every byte b
matches bit b of the ColorCompare register; other-
wise it is set to 0. There is a ColorDon’tCare register
that can exclude planes from this comparison. In
four-plane graphics modes, this provides a conver-
sion from 4 BPP to 1 BPP.
The ALU is a simple two-operand ROP unit that operates
on writes. Its operating modes are COPY, AND, OR, and
XOR. The 32-bit inputs are:
1) the output of the write-mode unit and
2) the display latch (not necessarily the value at the
frame buffer address of the write).
An application that wishes to performs ROPs on the
source and destination must first byte read the address (to
load the latch) and then immediately write a byte to the
same address. The ALU has no effect in Write Mode 1.
The bit mask unit does not provide a true bit mask.
Instead, it selects between the ALU output and the display
latch. The mask is an 8-bit value, and bit n of the mask
makes the selection for bit n of all four bytes of the result
(a zero selects the latch). No bit masking occurs in Write
Mode 1.
The VGA hardware of the GXm processor does not imple-
ment Write Mode 1 directly, but it can be indirectly imple-
mented by setting the BitMask to zero and the ALU mode
to COPY.
相關(guān)PDF資料
PDF描述
30046-23 Low Power Integrated x86-Compatible 32-Bit Geode GXLV Processor(低功耗集成兼容X86的32位 Geode GXLV技術(shù)處理器)
300471U Radial, -55dotc, long life wsitching-power
300CNQ SCHOTTKY RECTIFIER
300CNQ035 SCHOTTKY RECTIFIER
300CNQ040 SCHOTTKY RECTIFIER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
3004430 功能描述:DIN導(dǎo)軌式接線端子 UK 5-MTK RoHS:否 制造商:Phoenix Contact 類型:Feed Through Modular Terminal Block 位置/觸點(diǎn)數(shù)量:1 線規(guī)量程:26-14 電流額定值:5 A, 15 A 電壓額定值:300 V, 600 V 安裝風(fēng)格: 端接類型:Push-In
30044-44L 制造商:LENOX 功能描述:HOLE SAW BI-METAL 70MM
3004472 制造商:Phoenix Contact 功能描述:UK 5-HESI (5X20)
300448 功能描述:手工工具 RETAINING PIN RoHS:否 制造商:Molex 產(chǎn)品:Extraction Tools 類型: 描述/功能:Extraction tool
300449 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:HAND TOOL ASSEMBLY