Revision 3.1
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Processor Programming (
Continued
)
G
Table 3-11. Configuration Registers
Bit
Name
Description
Index C1h
CCR1 — Configuration Control Register 1 (R/W)
Default Value = 00h
7:3
2:1
RSVD
SMAC
Reserved
: Set to 0.
System Management Memory Access:
If = 00: SMM is disabled.
If = 01: SMI# pin is active to enter SMM. SMINT instruction is inactive.
If = 10: SMM is disabled.
If = 11: SMINT instruction is active to enter SMM. SMI# pin is inactive.
Note:
SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write this bit.
Reserved
: Set to 0.
Note:
Bits 1 and 2 are cleared to zero at reset.
0
RSVD
Index C2h
CCR2 — Configuration Control Register 2 (R/W)
Default Value = 00h
7
USE_SUSP
Enable Suspend Pins
:
If = 1: SUSP# input and SUSPA# output are enabled.
If = 0: SUSP# input is ignored.
Reserved
: This is a test bit that must be set to 0.
Reserved
: Set to 0.
Write-Through Region 1
:
If = 1: Forces all writes to the address region between 640 KB to 1 MB that hit in the on-chip cache
to be issued on the external bus.
Suspend on HALT
:
If = 1: CPU enters suspend mode following execution of a HALT instruction.
Lock NW Bit
:
If = 1: Prohibits changing the state of the NW bit (CR0[29]) (refer to Table 3-7 on page 45).
Set to 1 after setting NW.
Reserved:
Set to 0.
Note:
All bits are cleared to zero at reset.
6
5
4
RSVD
RSVD
WT1
3
SUSP_HLT
2
LOCK_NW
1:0
RSVD
Index C3h
CCR3 — Configuration Control Register 3 (R/W)
Default Value = 00h
7
LSS_34
Load/Store Serialize 3 GB to 4 GB
:
If = 1: Strong R/W ordering imposed in address range C0000000h to FFFFFFFFh:
Load/Store Serialize 2 GB to 3 GB
:
If = 1: Strong R/W ordering imposed in address range 80000000h to BFFFFFFFh:
Load/Store Serialize 1 GB to 2 GB
:
If = 1: Strong R/W ordering imposed in address range 40000000h to 7FFFFFFFh
Map Enable
:
If = 1: All configuration registers are accessible. All accesses to Port 22h are trapped.
If = 0: Only configuration registers Index C1h through CFh, FEh, FFh (CCRn, SMAR, DIRn) are
accessible. Other configuration registers (including PCR, SMHRn, GCR, VGACTL, VGAM0) are not
accessible.
Enable Suspend in SMM Mode
:
0 = SUSP# ignored in SMM mode.
1 = SUSP# recognized in SMM mode.
Reserved:
Set to 0.
NMI Enable:
If = 1: NMI is enabled during SMM.
If = 0: NMI is not recognized during SMM.
Note:
SMI_LOCK (CCR3[0]) must = 0 or the CPU must be in SMI mode to write to this bit.
SMM Register Lock:
If = 1: SMM Address Region Register (SMAR[31:0]), SMAC (CCR1[2]), USE_SMI (CCR1[1])
cannot be modified unless in SMM routine. Once set, SMI_LOCK can only be cleared by asserting
the RESET pin.
Note:
All bits are cleared to zero at reset.
6
LSS_23
5
LSS_12
4
MAPEN
3
SUSP_SMM_EN
2
1
RSVD
NMI_EN
0
SMI_LOCK