Revision 3.1
241
www.national.com
Index (
Continued
)
G
PCI Command (04h-05h)
PCI Control Function 1 (40h)
PCI Control Function 2 (41h)
Register
Revision Identification (08h)
Translation Type Bits 1
0
Vendor Identification (00h-01h)
PCI Configuration Registers 0CF8h-0CFBh
PCI Controller
CONFIG_ADDRESS
Configuration Cycles
PCI Arbiter
Space Control Registers
Special Cycles
X-Bus PCI Master
X-Bus PCI Slave
PCI Cycles
PCI Halt Command
PCI Interface Signals
Frame
Initiator Ready
Lock Operation
Multiplexed Address and Data
Multiplexed Command and Byte Enables
Parity
Parity Error
Request Lines
Target Ready
Target Stop
PCI Local Bus Specification
PCI Read Transactions
PCI Special Cycle Command
PCI Write Transactions
PCR Performance Control Register Index 20h
PERR
Pixel Arrangement Within a DWORD
Pointer and Index Registers
ECX Counter
EDI Destination Pointer
ESI Source Pointer
ESP Register
PUSH and POP Instructions
Power and Ground Connections and Decoupling
Power Management
3-Volt Suspend Mode
Advanced Power Management (APM)
CPU Suspend Command Registers
Initiating Suspend with HALT
Initiating Suspend with SUSP
Processor Serial Bus
Responding to a PCI Access During Suspend Mode 177
Serial Packet Transmission
Stopping the Input Clock
Suspend Mode and Bus Cycles
Suspend Modulation
Power Management Registers
PM_BASE (FFFF FF6Ch)
PM_CNTRL_CSTP (8508h-850Bh)
PM_CNTRL_TEN (8504h-8507h)
PM_MASK (FFFF FF7Ch)
PM_SER_PACK (850Ch-850Fh)
PM_STAT_SMI (8500h-8503h)
Power Planes
Power, Ground, No Connect
Ground (VSS)
157
157
157
156
157
156
157
156
155
155
155
155
156
155
155
155
162
164
27
27
28
26
26
26
28
28
27
27
162
162
164
163
50
28
135
40
40
40
40
40
182
174
174
174
174
176
175
179
179
178
175
174
179
179
179
179
179
179
179
36
–
37
32
Power, Ground, No Connect Signals
Ground (VSS)
No Connect (NC)
Power Connect (VCC2)
Power Connect (VCC3)
Voltage Detect(VOLDET)
Privilege Level Transfers
Privilege Levels (CPL, DPL and RPL)
Privilege Levels (I/O)
Processor Core Instruction Set
Clock Counts
Flags
Legend
Opcodes
Processor Initialization
Programming Interface
Protected Mode, Initialization and Transition
Protection
Current Privilege Level (CPL)
Descriptor Privilege Level (DPL)
Requested Privilege Level (RPL)
Protection - V86 Mode
R
Register Controls
Register Sets
Application
Flags Register
General Purpose Register
Instruction Pointer Register
Segment Registers
Flags Register
General Purpose
Data Registers
Pointer and Index Registers
Instruction Pointer
Selection Rules
Model Specific Register
System Register Set
Registers
Application Register
Model Specific Register
REQ
RESET
ROP (raster operation)
Row Address Strobe
CAS
CKE
RAS
RASA
RASB
WE
S
Scratchpad
2KB configurations
3KB configurations
SMM information
Scratchpad RAM
SDRAM Clocks
SDCLK_IN
SDCLK_OUT
Segment Register Selection Rules
Segment Registers
Serial Packet
CX5520
32
32
32
32
32
87
86
86
212
212
212
212
212
38
38
87
86
86
86
86
88
38
40
40
40
40
40
43
40
40
40
42
42
40
40
,
44
40
59
28
38
166
29
29
29
29
29
29
97
97
97
97
30
30
42
42
25