Revision 3.1
221
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Instruction Set (
Continued
)
G
SETL/SETNGE
Set Byte on Less/Not Greater or Equal
To Register/Memory
SETLE/SETNG
Set Byte on Less or Equal/Not Greater
To Register/Memory
SETNB/SETAE/SETNC
Set Byte on Not Below/Above or Equal/Not Carry
To Register/Memory
SETNBE/SETA
Set Byte on Not Below or Equal/Above
To Register/Memory
SETNE/SETNZ
Set Byte on Not Equal/Not Zero
To Register/Memory
SETNL/SETGE
Set Byte on Not Less/Greater or Equal
To Register/Memory
SETNLE/SETG
Set Byte on Not Less or Equal/Greater
To Register/Memory
SETNO
Set Byte on Not Overflow
To Register/Memory
SETNP/SETPO
Set Byte on Not Parity/Parity Odd
To Register/Memory
SETNS
S
et Byte on Not Sign
To Register/Memory
SETO
Set Byte on Overflow
To Register/Memory
SETP/SETPE
Set Byte on Parity/Parity Even
To Register/Memory
SETS
Set Byte on Sign
To Register/Memory
SGDT
Store GDT Register
To Register/Memory
SIDT
Store IDT Register
To Register/Memory
SLDT
Store LDT Register
To Register/Memory
STR
Store Task Register
To Register/Memory
SMSW
Store Machine Status Word
STOS
Store String
SHL
Shift Left Logical
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
SHLD
Shift Left Double
Register/Memory by Immediate
Register/Memory by CL
SHR
Shift Right Logical
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
SHRD
Shift Right Double
Register/Memory by Immediate
Register/Memory by CL
SMINT
Software SMM Entry
0F 9C [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 9E [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 93 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 97 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 95 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 9D [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 9F [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 91 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 9B [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 99 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 90 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 9A [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 98 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
1
h
0F 01 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
6
6
b,c
h
0F 01 [mod 001 r/m]
-
-
-
-
-
-
-
-
-
6
6
b,c
h
0F 00 [mod 000 r/m]
-
-
-
-
-
-
-
-
-
1
a
h
0F 00 [mod 001 r/m]
0F 01 [mod 100 r/m]
A [101w]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
4
2
a
h
h
h
4
2
b,c
b
D [000w] [mod 100 r/m]
D [001w] [mod 100 r/m]
C [000w] [mod 100 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
x
x
x
x
x
x
u
u
u
x
x
x
x
x
x
1
2
1
1
2
1
b
h
0F A4 [mod reg r/m] #
0F A5 [mod reg r/m]
u
-
-
-
x
x
u
x
x
3
6
3
6
b
h
D [000w] [mod 101 r/m]
D [001w] [mod 101 r/m]
C [000w] [mod 101 r/m] #
x
u
u
-
-
-
-
-
-
-
-
-
x
x
x
x
x
x
u
u
u
x
x
x
x
x
x
2
2
2
2
2
2
b
h
0F AC [mod reg r/m] #
0F AD [mod reg r/m]
0F 38
u
-
-
-
x
x
u
x
x
3
6
84
3
6
84
b
h
-
-
-
-
-
-
-
-
-
s
s
Table 9-27. Processor Core Instruction Set Summary (Continued)
Instruction
Opcode
Flags
Real
Mode
Prot’d
Mode
Real
Mode
Prot’d
Mode
O D I
F
F
T
F
S Z
F
A P C
F
F
F
F
F
Clock Count
(Reg/Cache Hit)
Notes