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| 型號： | 30044-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible with MMX Support 32-Bit Geode GXm Processor(低功耗集成兼容X86帶有MMX的32位 Geode GXm技術處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁數： | 74/244頁 |
| 文件大?。?/td> | 4496K |
| 代理商： | 30044-23 |
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74
Revision 3.1
Processor Programming (
Continued
)
G
3.10 INTERRUPTS AND EXCEPTIONS
The processing of either an interrupt or an exception
changes the normal sequential flow of a program by trans-
ferring program control to a selected service routine.
Except for SMM interrupts, the location of the selected
service routine is determined by one of the interrupt vec-
tors stored in the interrupt descriptor table.
True interrupts are hardware interrupts and are generated
by signal sources external to the processor. All exceptions
(including so-called software interrupts) are produced inter-
nally by the processor.
3.10.1 Interrupts
External events can interrupt normal program execution
by using one of the three interrupt pins on the GXm pro-
cessor:
Non-maskable Interrupt (NMI pin)
Maskable Interrupt (INTR pin)
SMM Interrupt (SMI# pin)
For most interrupts, program transfer to the interrupt rou-
tine occurs after the current instruction has been com-
pleted. When the execution returns to the original
program, it begins immediately following the interrupted
instruction.
The
NMI interrupt
cannot be masked by software and
always uses interrupt vector 2 to locate its service routine.
Since the interrupt vector is fixed and is supplied inter-
nally, no interrupt acknowledge bus cycles are performed.
This interrupt is normally reserved for unusual situations
such as parity errors and has priority over INTR interrupts.
Once NMI processing has started, no additional NMIs are
processed until an IRET instruction is executed, typically
at the end of the NMI service routine. If NMI is re-asserted
before execution of the IRET instruction, one and only one
NMI rising edge is stored and then processed after execu-
tion of the next IRET.
During the NMI service routine, maskable interrupts may
be enabled. If an unmasked INTR occurs during the NMI
service routine, the INTR is serviced and execution
returns to the NMI service routine following the next IRET.
If a HALT instruction is executed within the NMI service
routine, the CPU restarts execution only in response to
RESET, an unmasked INTR or a System Management
Mode (SMM) interrupt. NMI does not restart CPU execu-
tion under this condition.
The
INTR interrupt
is unmasked when the Interrupt
Enable Flag (IF, bit 9) in the EFLAGS register is set to 1.
Except for string operations, INTR interrupts are acknowl-
edged between instructions. Long string operations have
interrupt windows between memory moves that allow
INTR interrupts to be acknowledged.
When an INTR interrupt occurs, the processor performs
an interrupt-acknowledge bus cycle. During this cycle, the
CPU reads an 8-bit vector that is supplied by an external
interrupt controller. This vector selects which of the 256
possible interrupt handlers will be executed in response to
the interrupt.
The
SMM interrupt
has higher priority than either INTR or
NMI. After SMI# is asserted, program execution is passed
to an SMI service routine that runs in SMM address space
reserved for this purpose. The remainder of this section
does not apply to the SMM interrupts. SMM interrupts are
described in greater detail later in this section.
3.10.2 Exceptions
Exceptions are generated by an interrupt instruction or a
program error. Exceptions are classified as traps, faults or
aborts depending on the mechanism used to report them
and the restartability of the instruction which first caused
the exception.
A
Trap exception
is reported immediately following the
instruction that generated the trap exception. Trap excep-
tions are generated by execution of a software interrupt
instruction (INTO, INT3, INTn, BOUND), by a single-step
operation or by a data breakpoint.
Software interrupts can be used to simulate hardware
interrupts. For example, an INTn instruction causes the
processor to execute the interrupt service routine pointed
to by the nth vector in the interrupt table. Execution of the
interrupt service routine occurs regardless of the state of
the IF flag (bit 9) in the EFLAGS register.
The one byte INT3, or breakpoint interrupt (vector 3), is a
particular case of the INTn instruction. By inserting this
one byte instruction in a program, the user can set break-
points in the code that can be used during debug.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 3004430 | 功能描述:DIN導軌式接線端子 UK 5-MTK RoHS:否 制造商:Phoenix Contact 類型:Feed Through Modular Terminal Block 位置/觸點數量:1 線規(guī)量程:26-14 電流額定值:5 A, 15 A 電壓額定值:300 V, 600 V 安裝風格: 端接類型:Push-In |
| 30044-44L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 70MM |
| 3004472 | 制造商:Phoenix Contact 功能描述:UK 5-HESI (5X20) |
| 300448 | 功能描述:手工工具 RETAINING PIN RoHS:否 制造商:Molex 產品:Extraction Tools 類型: 描述/功能:Extraction tool |
| 300449 | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:HAND TOOL ASSEMBLY |
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