參數(shù)資料
型號: 37C672
廠商: SMSC Corporation
英文描述: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述: 增強的超級I / O控制器,快速紅外線
文件頁數(shù): 125/173頁
文件大?。?/td> 965K
代理商: 37C672
1-40
HARDWARE
3802 GROUP USER’S MANUAL
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the
machine cycle following the completion of the in-
struction that is currently in execution.
Figure 44 shows a timing chart after an interrupt
occurs, and Figure 45 shows the time up to execu-
tion of the interrupt processing routine.
Fig. 44 Timing chart after an interrupt occurs
Fig. 45 Time up to execution of the interrupt processing routine
Generation of interrupt request
Main routine
Interrupt processing routine
7 to 23 cycles
(At performing 8.0 MHz, 1.75 s to 5.75 s)
2 cycles
5 cycles
Start of interrupt processing
0 to 16 cycles
Waiting time for
post-processing
of pipeline
Stack push and
Vector fetch
T : at execution of DIV instruction (16 cycles)
T
: CPU operation code fetch cycle
: Vector address of each interrupt
: Jump destination address of each interrupt
: “0016” or “0116
SYNC
BL, BH
AL, AH
SPS
Data bus
Not used
PCH
PCL
PS
AL
AH
Address bus
S, SPS
S-2, SPS
S-1, SPS
PC
BL
BH
AL, AH
SYNC
RD
WR
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