3802 GROUP USER’S MANUAL
3-39
APPENDIX
3.5 List of registers
Operating mode of
Timer X/Timer Y
Timer mode
Pulse output mode
Event counter mode
Pulse width measurement mode
Table. 3.5.1 Function of CNTR0/CNTR1 edge switch bit
Fig. 3.5.13 Structure of Timer XY mode register
Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6)
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
Generation of CNTR0/CNTR1 interrupt request : Falling edge
(No effect on timer count)
Generation of CNTR0/CNTR1 interrupt request : Rising edge
(No effect on timer count)
Start of pulse output : From “H” level
Generation of CNTR0/CNTR1 interrupt request : Falling edge
Start of pulse output : From “L” level
Generation of CNTR0/CNTR1 interrupt request : Rising edge
Timer X/Timer Y : Count of rising edge
Generation of CNTR0/CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Count of falling edge
Generation of CNTR0/CNTR1 interrupt request : Rising edge
Timer X/Timer Y : Measurement of “H” level width
Generation of CNTR0/CNTR1 interrupt request : Falling edge
Timer X/Timer Y : Measurement of “L” level width
Generation of CNTR0/CNTR1 interrupt request : Rising edge
Function
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
B
At reset
R W
0
1
2
3
4
5
6
7
0
Timer XY mode register (TM)
Name
Timer X operating mode
CNTR0 active edge switch
bit
Timer Y operating mode
CNTR1 active edge switch
bit
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer X (refer to Table 3.5.1).
It depends on the operating mode
of the Timer Y (refer to Table 3.5.1 ).
b5 b4
Timer X count stop bit
[Address : 2316]
b1 b0
Timer Y count stop bit
0 : Count start
1 : Count stop
0 : Count start
1 : Count stop