參數(shù)資料
型號: 37C672
廠商: SMSC Corporation
英文描述: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述: 增強的超級I / O控制器,快速紅外線
文件頁數(shù): 28/173頁
文件大小: 965K
代理商: 37C672
APPLICATION
2.6 Processor mode
2-66
3802 GROUP USER’S MANUAL
Figure 2.6.4, Figure 2.6.5 and Figure 2.6.6 show a standard timing at 8 MHz (No-Wait).
Fig. 2.6.4 Read-cycle (OE access, SRAM)
Fig. 2.6.5 Read-cycle (OE access, EPROM)
Output enabled access time of M5M5256BP
Data bus setup time before RD of 3802
td(AH – RD)
RD pulse width of 3802
RD delay time after outputting address of 3802
50 ns (max)
65 ns (min)
Address (low-order)
A0–A7
(Port P0)
Address (high-order)
A8–A14
(Port P1)
,,,,,,,
Data
DQ1–DQ8
(Port P2)
S
(A15)
WR
“H ”
“”
level
125 ns - 10 ns (min)
125 ns - 35 ns (min)
OE
(RD of 3802)
td(AH – RD)
tWL(RD)
ta(OE)
tsu(DB – RD)
:
tWL(RD)
:
ta(OE)
:
tsu(DB – RD)
: RD delay time after outputting address of 3802
: Output enabled access time of M5M27C256AK
: Data bus setup time before RD of 3802
50 ns (max)
65 ns (min)
Address (low-order)
A0–A7
(Port P0)
Address (high-order)
A8–A14
(Port P1)
,,,,,,,
Data
D0–D7
(Port P2)
WR
H
level
CE
5.8 ns (max)
tPHL
125 ns - 10ns (min)
125 ns - 35 ns (min)
OE
(RD of 3802)
td(AH – RD)
tWL(RD)
ta(OE)
tsu(DB – RD)
: RD pulse width of 3802
ta(OE)
td(AH – RD)
tWL(RD)
tsu(DB – RD)
tPHL
Output delay time of 74F04
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