2-9
3802 GROUP USER’S MANUAL
APPLICATION
2.2 Timer
Fig. 2.2.7 Structure of Interrupt request register 2
Fig. 2.2.6 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset
RW
0
1
2
3
0
Interrupt request reigster 2 (IREQ2) [Address : 3D16]
Name
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Serial I/O2 interrupt request
bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
INT2 interrupt request bit
T
5
6
7
0
0 : No interrupt request
1 : Interrupt request
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
AD conversion interrupt
request bit
INT4 interrupt request bit
0 : No interrupt request
1 : Interrupt request
T
“0” is set by software, but not “1.”
T
4
0
0 : No interrupt request
1 : Interrupt request
INT3 interrupt request bit
T
0
!
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset RW
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
Name
“0” is set by software, but not “1.”
T
Timer Y interrupt request
bit
4
5
6
7
0
Timer X interrupt request
bit
Timer 1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
Timer 2 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
T
0
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O1 receive interrupt
request bit
Serial I/O1 transmit interrupt
request bit
0
1
2
3