參數(shù)資料
型號: 37C672
廠商: SMSC Corporation
英文描述: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述: 增強的超級I / O控制器,快速紅外線
文件頁數(shù): 4/173頁
文件大?。?/td> 965K
代理商: 37C672
2.3 Serial I/O
2-44
APPLICATION
3802 GROUP USER’S MANUAL
The communication is performed according to the timing shown below. In the slave unit, when a
synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is
processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.3.33 shows a setting of related registers.
Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers]
D0
Byte cycle
Block transfer period
Block transfer cycle
D1
D2
D7
D0
Interval between blocks
Processing for heading adjustment
Heading adjustive time
Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between
microcomputers]
Master unit
Transmit enabled
SIO1CON
Serial I/O1 control register (Address : 1A16)
Synchronous
clock : BRG/4
Transmit interrupt source :
Transmit shift operating completion
Receive enabled
Clock synchronous serial I/O
0
1
11
0
1
Serial I/O1 enabled
BRG count source : f(XIN)
Not use the SRDY1 output
Not be effected by
external clock
Transmit enabled
SIO1CON
Serial I/O1 control register (Address : 1A16)
Not use the serial I/O1 transmit interrupt
Receive enabled
Clock synchronous serial I/O
1
Slave unit
1
Serial I/O1 enabled
0
Synchronous clock : External clock
Not use the SRDY1 output
UARTCON
UART control register (Address : 1B16)
P45/TXD pin : CMOS output
0
Both of units
b7
b0
7
BRG
b7
b0
Baud rate generator (Address : 1C16)
Set “division ratio – 1”
b7
b0
b7
b0
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