參數(shù)資料
型號: 37C672
廠商: SMSC Corporation
英文描述: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述: 增強的超級I / O控制器,快速紅外線
文件頁數(shù): 148/173頁
文件大?。?/td> 965K
代理商: 37C672
APPLICATION
2.2 Timer
2-19
3802 GROUP USER’S MANUAL
Control procedure :
Figure 2.2.19 shows a control procedure.
Fig. 2.2.19 Control procedure [Measurement of frequency]
Timer 1 interrupt processing routine
RESET
IREQ1 (Address : 3C16), bit5?
Initialization
SEI
TM
PRE12
T1
PREY
TY
ICON1
TM
CLI
....
(Address : 2316)
(Address : 2016)
(Address : 2116)
(Address : 2616)
(Address : 2716)
(Address : 3E16), bit6
(Address : 2316), bit7
1110XXXX2
64–1
8–1
1–1
256–1
1
~
(A)
TY (Address : 2716)
TY
IREQ1
(Address : 2716)
(Address : 3C16), bit5
256 – 1
0
1
0
Fpulse
0
Fpulse
1
Processing for a result of judgment
RTI
Out of range
In range
Compare the count value read with the
reference value.
Store the comparison result in flag Fpulse.
q
CLT (Note 1)
CLD (Note 2)
Push register to stack
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
q
Push the register used in the interrupt
processing routine into the stack.
Pop registers
X
q
: This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
0
q
Read the count value.
Store the count value in the accumulator (A).
q
Initialize the count value.
Set the Timer Y interrupt request bit to “0.”
q
When the count value is 256 or more, the
processing is performed as out of range.
q
All interrupts : Disabled
Timer Y : Event counter mode
(Count at falling edge of pulse input from CNTR1 pin)
Set the division ratio so that the Timer 1 interrupt
occurs every 2 ms.
Timer 1 interrupt : Enabled
q
Timer Y count : Start
Interrupts : Enabled
<
214
(A)
228?
Pop registers which is pushed to stack.
q
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