參數(shù)資料
型號: 37C672
廠商: SMSC Corporation
英文描述: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述: 增強的超級I / O控制器,快速紅外線
文件頁數(shù): 92/173頁
文件大?。?/td> 965K
代理商: 37C672
1-10
3802 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Execute JSR
On-going Routine
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
Execute RTS
(PCL)
M (S)
(S)
(S – 1)
(S)
(S + 1)
(S)
(S + 1)
(PCH)
M (S)
Subroutine
Restore Return
Address
Store Return Address
on Stack (Note 2)
M (S)
(PS)
Execute RTI
(PS)
M (S)
(S)
(S – 1)
(S)
(S + 1)
Interrupt
Service Routine
Restore Contents of
Processor Status Register
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
(PCL)
M (S)
(S)
(S + 1)
(S)
(S + 1)
(PCH)
M (S)
Restore Return
Address
I Flag “0” to “1”
Fetch the Jump Vector
Store Return Address
on Stack (Note 2)
Store Contents of Processor
Status Register on Stack
Interrupt request
(Note 1)
Note 1 : The condition to enable the interrupt
Interrupt enable bit is “1”
Interrupt disable flag is “0”
2 : When an interrupt occurs, the address of the next instruction to be executed is stored in
the stack area. When a subroutine is called, the address one before the next instruction
to be executed is stored in the stack area.
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 8. Register push and pop at interrupt generation and subroutine call
Table. 4. Push and pop instructions of accumulator or processor status register
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