參數(shù)資料
型號: 37C672
廠商: SMSC Corporation
英文描述: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述: 增強(qiáng)的超級I / O控制器,快速紅外線
文件頁數(shù): 70/173頁
文件大小: 965K
代理商: 37C672
3802 GROUP USER’S MANUAL
3-35
APPENDIX
3.5 List of registers
Fig. 3.5.5 Structure of Serial I/O1 control register
Serial I/O1 synchronous clock
selection bit (SCS)
SRDY1
output enable bit
(SRDY)
Transmit interrupt
source selection bit (TIC)
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset RW
0
1
2
3
0 : f(XIN)
1 : f(XIN)/4
0
Serial I/O1 control register (SIO1CON) [Address : 1A16]
Name
BRG count source selection
bit (CSS)
4
5
6
7
0
Serial I/O1 enable bit (SIOE)
0 : I/O port (P47)
1 : SRDY1 output pin
Transmit enable bit (TE)
Receive enable bit (RE)
Serial I/O1 mode
selection bit (SIOM)
0 : Transmit buffer empty
1 : Transmit shift operating completion
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0 : UART
1 : Clock synchronous serial I/O
0 : Serial I/O1 disabled
(P44–P47
: I/O port)
1 : Serial I/O1 enabled
(P44–P47
: Serial I/O function pin)
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
At selecting UART
0 : BRG output divided by 16
1 : External clock input divided by 16
Fig. 3.5.6 Structure of UART control register
In output mode
0 : CMOS output
1 : N-channel open-drain output
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset
RW
0
1
2
3
0
UART control register (UARTCON) [Address : 1B16]
Name
0
1
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : 1 stop bit
1 : 2 stop bits
0 : Even parity
1 : Odd parity
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Stop bit length
selection bit (STPS)
Parity selection bit
(PARS)
P45/TxD P-channel
output disable bit (POFF)
5
6
7
4
Nothing is allocated for these bits. These are write disabled
bits. When these bits are read out, the values are “1.”
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