
viii
7540 Group User’s Manual
Fig. 2.7.11 Control procedure of transmission side ..............................................................2-126
Fig. 2.7.12 Control procedure of reception side....................................................................2-127
Fig. 2.8.1 Memory map of registers relevant to A-D converter ..........................................2-129
Fig. 2.8.2 Structure of A-D control register............................................................................2-129
Fig. 2.8.3 Structure of A-D conversion register (low-order).................................................2-130
Fig. 2.8.4 Structure of A-D conversion register (high-order) ...............................................2-130
Fig. 2.8.5 Structure of Interrupt request register 2 ...............................................................2-131
Fig. 2.8.6 Structure of Interrupt control register 2 ................................................................2-131
Fig. 2.8.7 Relevant registers setting .......................................................................................2-132
Fig. 2.8.8 Connection diagram .................................................................................................2-133
Fig. 2.8.9 Control procedure.....................................................................................................2-133
Fig. 2.8.10 Connection diagram ...............................................................................................2-134
Fig. 2.9.1 Memory map of registers relevant to oscillation control ....................................2-135
Fig. 2.9.2 Structure of MISRG .................................................................................................2-135
Fig. 2.9.3 Structure of Watchdog timer control register .......................................................2-136
Fig. 2.9.4 Structure of CPU mode register ............................................................................2-136
Fig. 2.9.5 Setting method when the ring oscillator is used as the operation clock.........2-137
Fig. 2.9.6 Control procedure.....................................................................................................2-138
Fig. 2.9.7 Initial setting method for the oscillation stop detection circuit ..........................2-140
Fig. 2.9.8 Setting method for the oscillation stop detection circuit in main processing ..2-141
Fig. 2.9.9 State transition..........................................................................................................2-142
Fig. 2.9.10 Example of mode transition..................................................................................2-143
Fig. 2.9.11 Control procedure...................................................................................................2-144
CHAPTER 3 APPENDIX
Fig. 3.1.1 Switching characteristics measurement circuit diagram (General purpose).......3-11
Fig. 3.1.2 Timing chart (General purpose) ...............................................................................3-12
Fig. 3.1.3
Switching characteristics measurement circuit diagram (Extended operating temperature)
3-20
Fig. 3.1.4 Timing chart (Extended operating temperature version) ......................................3-21
Fig. 3.1.5 Switching characteristics measurement circuit diagram (Extended operating temperature
125 °C version) .....................................................................................................................3-29
Fig. 3.1.6 Timing chart (Extended operating temperature 125 °C version).........................3-30
Fig. 3.2.1 V
CC
-I
CC
characteristics (in double-speed mode: Mask ROM version)..................3-31
Fig. 3.2.2 V
CC
-I
CC
characteristics (in high-speed mode: Mask ROM version) ......................3-31
Fig. 3.2.3 V
CC
-I
CC
characteristics (in middle-speed mode: Mask ROM version) ..................3-31
Fig. 3.2.4 V
CC
-I
CC
characteristics (at WIT instruction execution: Mask ROM version)........3-32
Fig. 3.2.5 V
CC
-I
CC
characteristics (at STP instruction execution: Mask ROM version) .......3-32
Fig. 3.2.6 V
CC
-I
CC
characteristics (addition when operating A-D conversion, f(X
IN
) = 8 MHz in
high-speed mode: Mask ROM version)..............................................................................3-33
Fig. 3.2.7 V
CC
-I
CC
characteristics (addition when operating A-D conversion, f(X
IN
) = 6 MHz in
double-speed mode: Mask ROM version) .........................................................................3-33
Fig. 3.2.8V
CC
-I
CC
characteristics (When system is operating by ring oscillator, Ceramic oscillation
stop: Mask ROM version) ....................................................................................................3-34
Fig. 3.2.9 V
CC
-I
CC
characteristics (When system is operating by ring oscillator, at WIT instruction
execution, Ceramic oscillation stop: Mask ROM version) ...............................................3-34
Fig. 3.2.10 f(X
IN
)-I
CC
characteristics (in double-speed mode: Mask ROM version).............3-35
Fig. 3.2.11 f(X
IN
)-I
CC
characteristics (in high-speed mode: Mask ROM version) .................3-35
Fig. 3.2.12 f(X
IN
)-I
CC
characteristics (in middle-speed mode: Mask ROM version) .............3-35
Fig. 3.2.13 f(X
IN
)-I
CC
characteristics (at WIT instruction execution: Mask ROM version)...3-36
Fig. 3.2.14 Ta-I
CC
characteristics (When system is operating by ring oscillator, Ceramic oscillation
stop: Mask ROM version) ....................................................................................................3-36
Fig. 3.2.15 Ta-I
CC
characteristics (When system is operating by ring oscillator, at WIT instruction
execution, Ceramic oscillation stop: Mask ROM version) ...............................................3-36
List of figures