
7540 Group User
’
s Manual
2-136
APPLICATION
2.9 Oscillation control
Fig. 2.9.3 Structure of Watchdog timer control register
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
1
1
2
3
4
5
6
7
Name
1
1
1
1
1
0
0
Watchdog timer control register (WDTCON) [Address : 39
16
]
Watchdog timer H
(The high-order 6 bits are read-only bits.)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
0 : Watchdog timer L underflow
1 : f(X
IN
)/16
Watchdog timer H count
source selection bit
Fig. 2.9.4 Structure of CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
2
3
4
5
6
7
Name
0
0
0
1
CPU mode register (CPUM) [Address : 3B
16
]
CPU mode register
0
0
0
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
b1 b0
1
0
Processor mode bits (
Note 1
)
0 : Ceramic oscillation
1 : RC oscillation
0 : 0 page
1 : 1 page
0 :
Ring oscillator oscillation enabled
1 : Ring oscillator oscillation stop
Stack page selection bit
Oscillation mode selection bit
(
Note 1
)
Clock division ratio selection
bits
0 0 :
φ
=
f(X
IN
)/2
(high-speed mode)
0 1 :
φ
=
f(X
IN
)/8
(middle-speed mode)
1 0 : Applied from ring oscillator
1 1 :
φ
=
f(X
IN
)
(double-speed mode)
(
Note 2
)
b7 b6
0 :
Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
Notes 1:
The bit can be rewritten only once after releasing reset. After rewriting it is
disable to write any data to the bit. However, by reset the bit is initialized and
can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“
M37540RSS
”
.)
2:
These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Ring oscillator oscillation
control bit
X
IN
oscillation control bit