
7540 Group User
’
s Manual
3-119
APPENDIX
3.5 List of registers
Fig. 3.5.38 Structure of Interrupt control register 2
Fig. 3.5.37 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
0
0
Interrupt control register 2 (ICON2) [Address : 3F
16
]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are
“
0
”
.
Timer Y interrupt
enable bit
Timer Z interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Timer 1 interrupt enable bit
Timer A interrupt enable bit
Serial I/O2 interrupt enable bit
AD conversion interrupt
enable bit
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16
]
Serial I/O1 receive
interrupt enable bit
Serial I/O1 transmit interrupt
enable bit
INT
0
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
INT
1
interrupt enable bit
Key-on wake up interrupt
enable bit
Timer X interrupt enable bit