APPENDIX
7540 Group User
’
s Manual
3-19
3.1 Electrical characteristics
(5) Timing Requirements (Extended operating temperature version)
Table 3.1.19 Timing requirements (1)
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min.
2
125
50
50
200
80
80
2000
800
800
800
370
370
220
100
1000
400
400
200
200
Typ.
Max.
Symbol
Parameter
Limits
Unit
Reset input
“
L
”
pulse width
External clock input cycle time
External clock input
“
H
”
pulse width
External clock input
“
L
”
pulse width
CNTR
0
input cycle time
CNTR
0
, INT
0
, INT
1
, input
“
H
”
pulse width
CNTR
0
, INT
0
, INT
1
, input
“
L
”
pulse width
CNTR
1
input cycle time
CNTR
1
input
“
H
”
pulse width
CNTR
1
input
“
L
”
pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input
“
H
”
pulse width (Note)
Serial I/O1 clock input
“
L
”
pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input
“
H
”
pulse width
Serial I/O2 clock input
“
L
”
pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR
0
)
t
WH
(CNTR
0
)
t
WL
(CNTR
0
)
t
C
(CNTR
1
)
t
WH
(CNTR
1
)
t
WL
(CNTR
1
)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(RxD
1
–
S
CLK1
)
t
h
(S
CLK1
–
RxD
1
)
t
C
(S
CLK2
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
su
(S
DATA2
–
S
CLK2
)
t
h
(S
CLK2
–
S
DATA2
)
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
In this time, bit 6 of the serial I/O1 control register (address 001A
16
) is set to
“
1
”
(clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is
“
0
”
(clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Table 3.1.20 Timing requirements (2)
(V
CC
= 2.4 to 5.5 V, V
SS
= 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min.
2
250
100
100
500
230
230
4000
1600
1600
2000
950
950
400
200
2000
950
950
400
400
Typ.
Max.
Symbol
Parameter
Limits
Unit
Reset input
“
L
”
pulse width
External clock input cycle time
External clock input
“
H
”
pulse width
External clock input
“
L
”
pulse width
CNTR
0
input cycle time
CNTR
0
, INT
0
, INT
1
, input
“
H
”
pulse width
CNTR
0
, INT
0
, INT
1
, input
“
L
”
pulse width
CNTR
1
input cycle time
CNTR
1
input
“
H
”
pulse width
CNTR
1
input
“
L
”
pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input
“
H
”
pulse width (Note)
Serial I/O1 clock input
“
L
”
pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input
“
H
”
pulse width
Serial I/O2 clock input
“
L
”
pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR
0
)
t
WH
(CNTR
0
)
t
WL
(CNTR
0
)
t
C
(CNTR
1
)
t
WH
(CNTR
1
)
t
WL
(CNTR
1
)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(RxD
1
–
S
CLK1
)
t
h
(S
CLK1
–
RxD
1
)
t
C
(S
CLK2
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
su
(S
DATA2
–
S
CLK2
)
t
h
(S
CLK2
–
S
DATA2
)
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
In this time, bit 6 of the serial I/O1 control register (address 001A
16
) is set to
“
1
”
(clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is
“
0
”
(clock asynchronous serial I/O1 is selected), the rating values are divided by 4.