
7540 Group User
’
s Manual
2-6
APPLICATION
2.1 I/O port
Fig. 2.1.8 Structure of Interrupt edge selection register
Fig. 2.1.9 Structure of Interrupt request register 1
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
0
0
Interrupt edge selection register (INTEDGE) [Address : 3A
16
]
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are
“
0
”
.
INT
0
interrupt edge
selection bit
INT
1
interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
P0
0
key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
0
0
Interrupt request register 1 (IREQ1) [Address : 3C
16
]
Serial I/O1 receive
interrupt request bit
Serial I/O1 transmit interrupt
request bit
INT
0
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
:
These bits can be cleared to
“
0
”
by program, but cannot be set to
“
1
”
.
INT
1
interrupt request bit
Key-on wake up interrupt
request bit
Timer X interrupt request bit