
HARDWARE
1-56
7540 Group User
’
s Manual
A-D Converter
A-D conversion is started by setting AD conversion
completion bit to
“
0.
”
During A-D conversion, internal
operations are performed as follows.
1. After the start of A-D conversion, A-D conversion
register goes to
“
00
16
.
”
2. The highest-order bit of A-D conversion register
is set to
“
1,
”
and the comparison voltage Vref is
input to the comparator. Then, Vref is compared
with analog input voltage V
IN
.
3. As a result of comparison, when Vref < V
IN
, the
highest-order bit of A-D conversion register be-
comes
“
1.
”
When Vref > V
IN
, the highest-order
bit becomes
“
0.
”
By repeating the above operations up to the lowest-
order bit of the A-D conversion register, an analog
value converts into a digital value.
A-D conversion completes at 122 clock cycles (20.34
μ
s at f(X
IN
) = 6.0 MHz) after it is started, and the
result of the conversion is stored into the A-D
conversion register.
Concurrently with the completion of A-D conversion,
A-D conversion interrupt request occurs, so that
the AD conversion interrupt request bit is set to
“
1.
”
Relative formula for a reference voltage V
REF
of A-D converter and Vref
When n = 0
Vref = 0
When n = 1 to 1023
Vref =
n
n : the value of A-D converter (decimal numeral)
V
REF
1024
1
–
10:
A
result of the first to tenth comparison
Table 9 Change of A-D conversion register during A-D conversion
At start of conversion
First comparison
Second comparison
Third comparison
After completion of
tenth comparison
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
REF
2
V
REF
2
V
REF
V
REF
4
V
REF
±
2
8
4
V
REF
±
±
A result of A-D conversion
1
1
2
1
2
3
4
5
6
7
8
Change of A-D conversion register
Value of comparison voltage (Vref)
FUNCTIONAL DESCRIPTION SUPPLEMENT
0
0
0
0
0
0
0
0
0
9
10
2
1024
4
V
REF
V
REF
V
REF
±
±
±