
7540 Group User
’
s Manual
3-102
APPENDIX
3.5 List of registers
Fig. 3.5.9 Structure of Serial I/O1 control register
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
1
2
3
4
5
6
7
Name
0
0
0
0
0
0
Serial I/O1 control register (SIO1CON) [Address : 1A
16
]
0 : f(X
IN
)
1 : f(X
IN
)/4
When clock synchronous serial I/O
is selected;
0: BRG output divided by 4
1: External clock input
When UART is selected;
0: BRG output divided by 16
1:
External clock input divided by 16
0: P1
3
pin
1: S
RDY1
output pin
BRG count source
selection bit (CSS)
Serial I/O1 synchronous clock
selection bit (SCS)
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0: Clock asynchronous (UART)
serial I/O
1: Clock synchronous serial I/O
Transmit interrupt
source selection bit (TIC)
Transmit enable bit (TE)
Receive enable bit (RE)
Serial I/O1 enable bit
(SIOE)
0 : Interrupt when transmit buffer
has emptied
1 : Interrupt when transmit shift
operation is completed
0: Serial I/O1 disabled
1: Serial I/O1 enabled
0
S
RDY1
output enable bit
(SRDY)
Serial I/O1 mode selection bit
(SIOM)
Fig. 3.5.10 Structure of UART control register
7 b
6 b5 b
4 b
3 b
2 b
1 b
0
B
0
Function
A
t
r
e
s
e
t
R W
1
2
3
4
5
6
7
N
e
n
i
t
b
l
a
g
C
b
m
t
h
H
i
t
e
A
0
0
0
0
1
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
C
O
N
)
[
A
d
d
r
e
s
s
:
1
B
1
6
]
N
W
o
t
h
e
i
n
n
g
t
h
i
e
s
a
e
l
l
o
b
c
i
t
a
s
t
a
e
d
r
e
f
o
r
e
r
a
t
h
d
e
o
s
u
e
t
,
b
t
i
h
t
s
e
.
v
T
a
h
l
e
u
s
e
e
s
a
a
r
r
e
e
w
“
r
i
”
t
.
e
d
i
s
a
b
l
e
d
b
i
t
s
.
h
s
1
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
C
s
P
(
P
P
(
P
h
e
a
a
e
r
A
r
A
r
c
t
R
i
t
R
a
t
y
E
y
S
c
i
o
e
t
e
n
n
r
a
l
l
b
(
S
)
i
e
)
S
b
P
o
(
t
o
t
p
(
S
b
T
T
u
F
i
P
x
t
F
t
l
S
D
d
)
e
n
)
P
i
s
g
t
h
s
e
l
e
c
t
i
o
n
i
a
s
)
e
l
e
c
t
i
o
n
b
i
t
In
0
1
:
:
o
C
N
o
u
t
M
-
c
u
p
u
O
h
p
t
S
a
u
m
n
t
o
u
n
e
d
t
l
e
p
o
o
u
p
t
e
n
-
d
r
a
i
n
t
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
1
1
/
u
P
-
c
b
h
l
e
a
n
b
n
i
t
e
l
t
O
p
a
1
1
0