
7540 Group User’s Manual
3-87
APPENDIX
(3) Structure of interrupt control register 2
Fix the bit 7 of the interrupt control register 1 to “0”. Figure 3.3.7 shows the structure of the interrupt
control register 2.
Fig. 3.3.7 Structure of interrupt control register 2
0
b7
b0
Interrupt control register 2 (address: 003F
16
)
Interrupt enable bit
Not used (fix this bit to “0”)
(4) Interrupt
When setting the followings, the interrupt request bit may be set to “1”.
When switching external interrupt active edge
Related register: Interrupt edge selection register (address 003A
16
)
Timer X mode register (address 002B
16
)
Timer A mode register (address 001D
16
)
When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit (active edge switch bit).
Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
3.3.14 Notes on RESET pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V
SS
pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
Make the length of the wiring which is connected to a capacitor as short as possible.
Be sure to verify the operation of application products on the user side.
G
Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3 Notes on use