7540 Group User
’
s Manual
3-105
APPENDIX
3.5 List of registers
Fig. 3.5.13 Structure of Timer A register
Fig. 3.5.14 Structure of Timer Y, Z mode register
Timer A register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
1
1
2
3
4
5
6
7
1
1
1
1
1
1
1
Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E
16
, 1F
16
]
Set a count value of timer A.
The value set in this register is written to both timer A and timer A
latch at the same time.
When this register is read out, the timer A
’
s count value is read
out.
Notes 1:
Be sure to write to/read out both the low-order of timer A (TAL) and the high-
order of timer A (TAH).
2:
Read the high-order of timer A (TAH) first, and the high-order of timer A (TAL) next.
3:
Write to the low-order of timer A (TAL) first, and the high-order of timer A (TAH) next.
4:
Do not write to them during read, and do not read out them during write.
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
4
5
6
7
Name
0
0
0
0
0
0
0
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is
“
0
”
.
Timer Y write control bit
(
Note
)
Timer Y, Z mode register (TYZM) [Address : 20
16
)
Timer Y operating mode bit
0 : Timer mode
1 : Programmable waveform
generation mode
0 : Write to latch and timer
simultaneously
1 : Write to only latch
0 : Count start
1 : Count stop
Timer Y count stop bit
Timer Z operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Programmable waveform
generation mode
1 0 : Programmable one-shot
generation mode
1 1 : Programmable wait one-shot
generation mode
0 : Write to latch and timer
simultaneously
1 : Write to only latch
0 : Count start
1 : Count stop
Timer Z write control bit
(
Note
)
Timer Z count stop bit
Note
: When modes other than the timer mode, set these bits to
“
1
”
.