xxiv
82801BA ICH2
Datasheet
5-73
5-74
5-75
5-76
5-77
5-78
5-79
5-80
5-81
5-82
5-83
5-84
5-85
5-86
5-87
5-88
5-89
5-90
5-91
5-92
5-93
6-1
6-2
6-3
6-4
7-1
7-2
7-3
7-4
7-5
7-6
8-1
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
10-1
10-2
11-1
11-2
11-3
SOF Packet ..............................................................................................5-113
Data Packet Format..................................................................................5-114
Bits maintained in low power states..........................................................5-117
USB Legacy Keyboard State Transitions .................................................5-119
Quick Protocol ..........................................................................................5-121
Send / Receive Byte Protocol...................................................................5-121
Write Byte/Word Protocol .........................................................................5-122
Read Byte/Word Protocol.........................................................................5-122
Process Call Protocol ...............................................................................5-123
Block Read/Write Protocol........................................................................5-125
I
2
C Block Read .........................................................................................5-126
Slave Write Cycle Format.........................................................................5-128
Slave Write Registers...............................................................................5-129
Command Types ......................................................................................5-129
Read Cycle Format...................................................................................5-130
Data Values for Slave Read Registers .....................................................5-131
Featured Supported by ICH2....................................................................5-132
AC’97 Signals...........................................................................................5-134
Input Slot 1 Bit Definitions.........................................................................5-139
Output Tag Slot 0......................................................................................5-140
AC-link state during PCIRST# ..................................................................5-143
PCI Devices and Functions ..........................................................................6-2
Fixed I/O Ranges Decoded by ICH2 ............................................................6-3
Variable I/O Decode Ranges........................................................................6-5
Memory Decode Ranges from Processor Perspective.................................6-6
PCI Configuration Map (LAN Controller—B1:D8:F0)....................................7-1
Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM....7-6
Data Register Structure ..............................................................................7-10
ICH2 Integrated LAN Controller CSR Space..............................................7-10
Self-Test Results Format............................................................................7-15
Statistical Counters.....................................................................................7-20
PCI Configuration Map (HUB-PCI—D30:F0)................................................8-1
PCI Configuration Map (LPC I/F—D31:F0) ..................................................9-1
DMA Registers............................................................................................9-23
PIC Registers..............................................................................................9-33
APIC Direct Registers.................................................................................9-41
APIC Indirect Registers ..............................................................................9-41
RTC I/O Registers ......................................................................................9-47
RTC (Standard) RAM Bank........................................................................9-47
PCI Configuration Map (PM—D31:F0) .......................................................9-53
APM Register Map......................................................................................9-58
ACPI and Legacy I/O Register Map............................................................9-59
TCO I/O Register Map................................................................................9-75
Summary of GPIO Implementation.............................................................9-81
Registers to Control GPIO..........................................................................9-83
PCI Configuration Map (IDE—D31:F1).......................................................10-1
Bus Master IDE I/O Registers...................................................................10-11
PCI Configuration Map (USB—D31:F2/F4)................................................11-1
USB I/O Registers ......................................................................................11-8
Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop
(Bit 0) Operation .......................................................................................11-10
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