I/O Register Index
A-4
Intel
82801BA ICH2 Datasheet
Advanced Power Management
Control Port Register
B2h
Section 9.8.2.1, “APM_CNT—Advanced Power
Management Control Port Register” on page 9-58
Advanced Power Management
Status Port Register
B3h
Section 9.8.2.2, “APM_STS—Advanced Power
Management Status Port Register” on page 9-58
Aliased at A0h–A1h
B4h–B5h
Aliased at A0h–A1h
B8h–B9h
Aliased at A0h–A1h
BCh–BDh
Channel 4 DMA Base & Current
Address Register
C0h
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Aliased at C0h
C1h
Channel 4 DMA Base & Current
Count Register
C2h
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Aliased at C2h
C3h
Channel 5 DMA Base & Current
Address Register
C4h
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Aliased at C4h
C5h
Channel 5 DMA Base & Current
Count Register
C6h
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Aliased at C6h
C7h
Channel 6 DMA Base & Current
Address Register
C8h
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Aliased at C8h
C9h
Channel 6 DMA Base & Current
Count Register
CAh
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Aliased at CAh
CBh
Channel 7 DMA Base & Current
Address Register
CCh
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Aliased at CCh
CDh
Channel 7 DMA Base & Current
Count Register
CEh
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Aliased at CEh
CFh
Channel 4–7 DMA Command
Register
Channel 4–7 DMA Status Register
D0h
Section 9.2.4, “DMACMD—DMA Command Register”
on page 9-26
Section 9.2.5, “DMASTS—DMA Status Register” on
page 9-26
Aliased at D0h
D1h
Channel 4–7 DMA Write Single
Mask Register
D4h
Section 9.2.6, “DMA_WRSMSK—DMA Write Single
Mask Register” on page 9-27
Aliased at D4h
D5h
Channel 4–7 DMA Channel Mode
Register
D6h
Section 9.2.7, “DMACH_MODE—DMA Channel Mode
Register” on page 9-27
Aliased at D6h
D7h
Channel 4–7 DMA Clear Byte
Pointer Register
D8h
Section 9.2.8, “DMA Clear Byte Pointer Register” on
page 9-28
Aliased at D8h
D9h
Table A-1. ICH2 Fixed I/O Registers (Continued)
Register Name
Port
EDS Section and Location
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