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參數(shù)資料
| 型號： | 82C836A-20 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁數(shù)： | 144/205頁 |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836A-20 |
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Local DRAM Bank Switch (SRA Mode)
Figure 11-7 shows CPU accesses to local DRAM in zero wait state mode with -RAS
initially high. These timing relationships apply when the DRAM bank needs to be
accessed is different from the bank for which -RAS was already active. Since -RAS for
the desired bank was already high, no further -RAS precharge time is required for the
desired bank. The basic protocol is the same as for CAS-only cycles, except as follows:
-RAS for the target bank goes active at the middle of TS, and -RAS for the previously
active bank simultaneously goes inactive.
Row address is valid for one PROCCLK before and after -RAS goes active.
If encoded RAS is being used, -RAS3 goes inactive at the middle of TS; one PROCCLK
later, RAS0-2 change to the new value; after one more PROCCLK, -RAS3 again goes
active. The net penalty for encoded RAS is one T-state (only for bank switch cycles).
These diagrams also apply if no -RAS was previously active. This can happen during the
first local memory access following a refresh or DMA cycle, or following a RAS timeout.
The minimum bank switch cycle for nonencoded RAS consists of T1P, T2P, T2P (three
T-states). For encoded RAS, an extra T2P is needed. For nonpipelined operation, an
extra T1 occurs at the beginning of the cycle. As with CAS-only cycles, a CAS Extend
wait state can also be enabled. An early wait state can also be enabled for EMS or
external cache support. Minimum -CAS active time is two PROCCLK cycles for write,
or three PROCCLK cycles for read.
The minimum time allowed for read data access from -RAS active is five PROCCLK
cycles.
Local DRAM RAS High Cycle (MRA Mode)
In MRA mode, bank-switch timing differs from SRA mode as follows:
RAS for the new bank frequently is already low, and the row address previously latched
by the DRAMs is already valid. In that case, bank switch timing is exactly the same as
page hit timing shown in Figure 11-6. The fastest possible bank-switch read in MRA
mode is two T-states, while the fastest possible bank-switch write in MRA mode is three
T-states (CPU running in pipeline mode).
If RAS for the new bank is not already low, then the cycle follows the nonencoded RAS
timing shown in Figure 11-7, except that RAS for the previously accessed bank remains
low instead of going high at mid-TS.
MRA mode, therefore, saves one T-state over SRA mode for bank-switch (page-hit)
DRAM reads. Since the majority of DRAM accesses will be reads (mostly code fetches),
and will be DRAM page-hits, the total reduction in T-states can be substantial. This the
key performance advantage of MRA mode over SRA.
I
CPU Access to AT-Bus
System Timing Relationships
11-12
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A/B | 制造商: 功能描述: 制造商:undefined 功能描述: |
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